1. Addressing Modes MTT48 3 - 16 CPU08 Core Motorola CPU08 ADDRESSING MODES

3. Addressing Modes MTT48 3 - 18 CPU08 Core Motorola Inherent Immediate Direct Extended Indexed Relative Memory to Memory ADDRESSING MODES

4. Addressing Modes MTT48 3 - 19 CPU08 Core Motorola Inherent Addressing Has no operand Operates mostly on CPU registers or bits Example: CLRA * opcode location Memory program space data space ocl* ocl + 1 4 F X A CPU 0 X

5. Addressing Modes MTT48 3 - 20 CPU08 Core Motorola Immediate Addressing Specifies value directly, not an address of the value Indicated by # Has one operand Contained in the byte or bytes immediately following opcode Example: LDA#$FF Memory program space data space ocl ocl + 1 A 6 F X A CPU F X

6. Addressing Modes MTT48 3 - 21 CPU08 Core Motorola Direct Addressing Specifies 8 bit address of operand Upper byte of 16 bit address is assumed to be $00 Used to access first 256 bytes of memory Address contained in the byte immediately following opcode Example: LDA$50 Memory program space data space ocl ocl + 1 B 6 5 0 X A 0050 0051 A CPU A X

7. Addressing Modes MTT48 3 - 22 CPU08 Core Motorola Extended Addressing Specifies 16 bit address of operand Used to access address greater $00FF memory Address contained in the two bytes immediately following opcode Example: LDA$0400 Memory program space data space ocl ocl + 1 C 6 0 4 X A 0400 0401 ocl + 20 A CPU X A

8. Addressing Modes MTT48 3 - 23 CPU08 Core Motorola Indexed Addressing - NO Offset - Specifies H:X index register contains the address of the operand Example: CLR,X CPU H:X 0400 Memory program space ocl ocl + 1 7 F X data space X 0400 ocl + 2X 0 0400

9. Addressing Modes MTT48 3 - 24 CPU08 Core Motorola Indexed Addressing - 8 Bit Offset- Unsigned 8 bit offset + unsigned H:X register = memory location H:X register is unaffected 8 bit offset is the byte immediately following opcode Example: CLR10,X CPU H:X 0400 Memory program space ocl ocl + 1 6 F 0 A data space X 040A ocl + 2X 0 040A

10. Addressing Modes MTT48 3 - 25 CPU08 Core Motorola Indexed Addressing - 16 Bit Offset - Unsigned 16 bit offset + unsigned H:X register = memory location H:X register is unaffected 16 bit offset is the two bytes immediately following opcode Example: STA$0100,X Memory program space ocl ocl + 1 D 7 0 1 data space X 0150 ocl + 20 5 0150 CPU H:X 0050 55 A

11. Addressing Modes MTT48 3 - 26 CPU08 Core Motorola Indexed Addressing - 8 & 16 Bit Offsets - Commonly used to access elements of data structures Offset would be base address of structure Index register would contain displacement to the Nth element ORG$100 TableFCB$10, $20, $30, $40....... * Calculate displacement for element N in A CLRH TAX LDATable,X NOTE: If Table were in the first 256 bytes of memory, most assemblers would use an 8-bit offset instruction element 1 0100 Table H:X=N element 1 element 2 element 3 element n element n+1 element n+2 element n+3

12. Addressing Modes MTT48 3 - 27 CPU08 Core Motorola Indexed Addressing - Using Stack pointer and 8-Bit Offset - Unsigned 8 bit offset + unsigned SP register = memory location SP register is unaffected 8 bit offset is the byte immediately following opcode bytes Example: STA5,SP Memory program space ocl ocl + 1 9 E E 7 stack space X 00D0 ocl + 20 5 F 00D5 CPU SP 00D0 FF A

13. Addressing Modes MTT48 3 - 28 CPU08 Core Motorola Indexed Addressing - Using Stack pointer and 16-Bit Offset - Unsigned 16 bit offset + unsigned SP register = memory location SP register is unaffected 16 bit offset is the two bytes immediately following opcode bytes Example: STA$100,SP CPU SP 00D0 FF A Memory program space ocl ocl + 1 9 E D 7 data space X 00D0 ocl + 20 1 F 01D0 0 ocl + 3 NOTE: If interrupts are disabled, SP can be used as an additional index register Less efficient because of pre byte

14. Addressing Modes MTT48 3 - 29 CPU08 Core Motorola Stack Pointer - 8 Bit Offsets - High level language support Compilers often place parameters for procedures and temporary storage on the stack Stack Pointer addressing is an efficient means to access this information 00C0 SPX temp 1 temp 2 msb temp 2 lsb param 3 param 2 param 1 temp 1 = 1,SP temp 2 = 2,SP and 3,SP param 3 = 4,SP param 2 = 5,SP param 1 = 6,SP What happens if the stack pointer moves? ie: more information is pushed onto the stack. Where is -1,SP ?

15. Addressing Modes MTT48 3 - 30 CPU08 Core Motorola Relative Addressing

16. Addressing Modes MTT48 3 - 31 CPU08 Core Motorola Relative Addressing Cont. Used in all conditional branch instructions If condition is TRUE Program Counter = Program Counter + Signed 8 bit offset else Program Counter is unaffected Example: BEQ$8100 CPU PC 8152 Memory program space $8150 $8151 2 7 A E $8152X 8100 if condition true

17. Addressing Modes MTT48 3 - 32 CPU08 Core Motorola Indexed Addressing - No Offset with Post Increment - Specifies H:X index register contains the address of the operand After address of operand is calculated, H:X is incremented by 1 Example: LoopCBEQX+,Out BRALoop Out.... Memory program space ocl ocl + 1 7 1 0 2 data space X 0400 ocl + 2X 5 0410 CPU H:X 0400 0401 0402 0411 55 A

18. Addressing Modes MTT48 3 - 33 CPU08 Core Motorola Indexed Addressing - 8 bit Offset with Post Increment - Just like indexed addressing with 8 bit offset, plus post increment After address of operand is calculated, H:X is incremented by 1 Example: LoopCBEQ$50,X+,Out BRALoop Out.... ocl + 1 ocl + 2 Memory program space ocl7 1 5 0 data space X 0450 0 2 5 0460 CPU H:X 0400 0401 0402 0411 55 A

19. Addressing Modes MTT48 3 - 34 CPU08 Core Motorola Memory to Memory Addressing Used to move information from one location to another Does not use/affect CPU registers –Except when using indexed addressing with post increment More efficient than Load/Store combination Can only be used with the MOV instruction MOVSource Address,Destination Address Four variations: Immediate to Direct Direct to Direct Indexed to Direct with Post Increment Direct to Indexed with Post Increment

20. Addressing Modes MTT48 3 - 35 CPU08 Core Motorola Source is one byte immediate value Destination must be in first 256 bytes of memory Example usage: Initialization of variables or registers Memory to Memory Addressing - Immediate to Direct - MOV#$AA,$F0 Memory program space ocl ocl + 1 6 E A ocl + 2F 0 data space X 00F0 A 00F0

21. Addressing Modes MTT48 3 - 36 CPU08 Core Motorola Source must be in first 256 bytes of memory Destination must be in first 256 bytes of memory Example usage: Moving data from one page zero location to another Memory to Memory Addressing - Direct to Direct - MOV$00,$F0 Memory program space ocl ocl + 1 4 E 0 ocl + 2F 0 data space X 00F0 5 00F0 data space 5 0000

22. Addressing Modes MTT48 3 - 37 CPU08 Core Motorola Memory to Memory Addressing - Indexed with Post Increment to Direct - MOVX+,$18 Memory program space ocl ocl + 1 7 E 1 8 ocl + 2X data space 5 0 0400 Source may be any where in memory map Destination must be in first 256 byte of memory Example usage: Writing data to a communications device from a buffer CPU H:X 0400 0401 X 0018 5 0 0018 data space

23. Addressing Modes MTT48 3 - 38 CPU08 Core Motorola Memory to Memory Addressing - Direct to Indexed with Post Increment - MOV$18,X+ Memory program space ocl ocl + 1 5 E 1 8 ocl + 2X data space 5 0 0018 Source must be in first 256 byte of memory Destination may be any where in memory map Example usage: Writing data from a communications device to a buffer CPU H:X 0400 0401 X 0400 5 0 0400 data space

24. Addressing Modes MTT48 3 - 39 CPU08 Core Motorola MEMORY TO MEMORY - EXAMPLE - SCI communication handling routines ORG$50 RCVPTRRMB2 XMTPTRRMB2 ORG$100 RCVBRMB10 XMTBRMB10 Receive LDHXRCVPTR MOV$18,X+ STHXRCVPTR Transmit LDHXXMTPTR MOVX+,$18 STHXXMTPTR RCVPTR 0100 XMTPTR 010A

25. Addressing Modes MTT48 3 - 40 CPU08 Core Motorola Addressing Modes Summary MODEExample Usage InherentPULX ImmediateADD#$10 DirectSUB$50 ExtendedSUB$200 Indexed no offsetSTA,X 8 or 16 bit offsetLDX$200,X post incrementCBEQX+,There 8 bit offset w/ post incCBEQ$50,X+,There Stack Pointer 8 or 16 bit offsetCLR5,SP Relative (PC)BEQHere Memory to Memory Immediate to DirectMOV#$00,$A0 Direct to DirectMOV$18,$F0 Indexed post inc to DirectMOVX+,$12 Direct to Indexed post incMOV$12,X+

26. Addressing Modes MTT48 3 - 41 CPU08 Core Motorola Address Modes Exercises For each operation, complete the instruction using the appropriate addressing mode. Also indicate the length (# of bytes) of the instruction and execution time (# of cycles). 1. Load accumulator A with the hex value 55. 2. Load the X register with the contents of memory location hex C1. 3. Load the X register with the contents of the memory location whose address is the contents of the X register. 4. Load accumulator A with the contents of the memory location whose address is the contents of X register higher than the memory address $220. HC08-addrSol Instruction: Operand: Bytes: Cycles: LDA LDX LDA 5. Normal branch instructions can change the program counter to an address as far as bytes forward or bytes backward in program memory relative to the address of the branch opcode. 6. Indexed addressing generates a memory address that is the sum of two values: a register and an offset. The register value is a (constant/variable) and the offset value is a (constant/variable). 7. Direct and Extended address modes generate a (constant/variable) address. Direct requires a (one/two) byte address in program memory whose value is from to ; Extended requires a (one/two) byte address in program memory whose value is from to. 8. A common way to use the 16-bit offset with index address mode is to use the (offset, X register) as the starting address to a table of items and the (offset, X register) as the distance to select the item to be accessed.