1. CHAPTER 6 Field Effect Transistors (FETs)
By: Dr Rosemizi Abd Rahim
Click here to watch the FETs animation video

2. Objectives
Explain the operation and characteristics of junction field effect transistors (JFET).
Understand JFET parameters
Discuss and analyze how JFETs are biased
Explain the operation and characteristics of metal oxide semiconductor field effect transistors (MOSFET)
Discuss and analyze how MOSFET are biased
Troubleshoot FET circuits.

3. Introduction
FET – a three-terminal voltage-controlled device used in amplification and switching application.
Field effect transistors controls current by voltage applied to the gate. The FET’s major advantage over the BJT is high input resistance.
2 basic type of FET: JFET and MOSFET

4. JFET
The junction field effect transistor, like a BJT, controls current flow. The difference is the way this is accomplished. The JFET uses voltage to control the current flow. As you will recall the transistor uses current flow through the base-emitter junction to control current. JFETs can be used as an amplifier just like the BJT.
Fig 7-10 basic JFET circuit
VGG voltage levels control current flow in theVDD, RD circuit.

5. JFET The terminals of a JFET are the source, gate, and drain.
A JFET can be either p channel or n channel.
Fig 7-1 simplified & 7-4 schem. symbol

6. JFET VDD provide a drain-to-source voltage.
VGG sets the reverse-bias voltage between gate and source. JFET is always operated with gate-source pn junction reverse-biased. Reverse-biasing of the gate-source junction with a –ve gate voltage produces a depletion region along pn junction.
Fig 7-2a JFET fwd biased
please label terminals

7. JFET Biasing
Gate-to-source junction of JFET always reverse-biased under normal condition.
Gate-to-source junction never allowed to become forward-biased because the gate material is not designed to handle any significant amount of current  may destroy the component.
The fact gate is always reverse-biased leads to important feature  JFET has high gate input impedance; typically in high megaohm range.
This feature result to JFET extensively being used in integrated circuits. Low current draw helps IC remain cool, thus allowing more components to be placed in a smaller physical area.

8. The JFET is always operated with the gate-source pn junction reverse-biased.
Reverse biasing of the gate-source junction with a negative gate voltage produces a depletion region
along the pn junction, which extends into the n channel
thus increases its resistance by restricting the channel width.
The channel width and the channel resistance can be controlled by varying the gate voltage, thereby controlling the amount of drain current, ID.

9. The white areas represent the depletion region created by the reverse bias. It is wider
toward the drain end of the channel because the reverse-bias voltage between the gate and
the drain is greater than that between the gate and the source.
R meningkat=V(meningkat)/I (menurun)

10. JFET Characteristics and Parameters
Let’s first take a look at the effects with a VGS of 0V. This is produced by shorting the gate to source junction.
Fig 7-5a & b JFET circ. & drain curve
# show Vds,Vdd,Vgd, Vgs

11. JFET Drain Curve

12. Refer to JFET drain curve from point A to B, ID increases proportionally with increases of VDD (VDS increases as VDD increases).
In this area, the channel resistance is essentially constant because the depletion region is not large enough to have significant effect. [V=IR]
This is called the ohmic region (point A to B) because VDS and ID are related by Ohm’s Law.

13. At point B, the curve levels off and ID becomes constant.
The point when ID ceases to increase regardless of VDD increases is called the pinch-off voltage, VP (point B).
This current is called maximum drain current (IDSS) and always specified for the condition, VGS=0V. This area is called constant-current area.
Breakdown (point C) occur when ID begins to increase rapidly with any increase in VDS. This of course undesirable, so JFETs operation is always well below this value.

14. Illustration of JFET Drain Curve
Fig 7-5a & b JFET circ. & drain curve

15. JFET Characteristics and Parameters
From this set of curves you can see with increased voltage applied to the gate, ID decrease and JFET reaches pinch-off at values of VDS less than VP.
Fig. 7-7a & b JFET circuit & curves

16. JFET Characteristics and Parameters
Fig. 7-7a & b JFET circuit & curves

17. JFET Characteristics and Parameters
Fig. 7-7a & b JFET circuit & curves

18. JFET Characteristics and Parameters
We know that as VGS is increased ID will decrease. The point that ID ceases decrease is called cutoff. The amount of VGS required to do this is called the cutoff voltage (VGS(off ) ).
The more negative VGS, the smaller ID becomes. When VGS has sufficiently large negative value, ID is reduced to zero.
It is interesting to note that pinch-off voltage (Vp) and cutoff voltage (VGS(off)) are both the same value only opposite polarity.
Fig 7-9 JFET cutoff
#When VGS has a sufficiently large negative value, ID is reduced
to zero. This cutoff effect is caused by the widening of the depletion region to a point
where it completely closes the channel.

19. JFET Transfer Characteristic
For n-channel JFET, VGS(off) is negative and for p-channel, VGS(off) is positive.
Bottom end of the curve is at a point on VGS axis equal to VGS(off) and the top end of the curve is at a point on ID axis equal to IDSS (shorted-gate drain current rating of the device).
The operating limits of JFET are:
ID=0 when VGS=VGS(off)
ID=IDSS when VGS = 0
Transfer characteristic curve can be developed from drain characteristic curves by plotting values of ID for the values of VGS taken from the family of drain curves at pinch-off.
Show example 8-1 (pg391)

20. JFET Characteristics and Parameters
The transfer characteristic curve illustrates the control VGS has on ID from cutoff (VGS(off) ) to pinchoff (VP). Note the parabolic shape. The formula below can be used to determine drain current. All these values are usually available from data sheet.
ID = IDSS(1 - VGS/VGS(off))2
Fig 7-13 transfer curve

21. JFET Forward Transfer Conductance
Forward transfer conductance, gm of JFETs is the changes in ID based on changes in VGS with VDS is constant.
Forward transfer conductance referred to as
gm = ∆ID /∆VGS.
Unit is Siemens (s)
The value is larger at the top of the curve (near VGS=0) but become smaller as you increase VGS (near VGS(off)).

22. Transconductance
At VGS =0, the parameter is known as minimum transfer conductance, gmo and can be calculated using this equation:
gmo = 2IDSS/|VGS(off)| and
gm = gmo(1 - VGS/VGS(off))
gmo can be read from the datasheet as gfs or yfs and sometimes written as Forward Transfer Admittance.

23. Example

24. JFET Input Resistance
Since JFET is reverse-biased for operation, its input resistance becomes so large. This is an advantage of using JFET. Looking at the datasheet, you may calculate the resistance value by using the Gate Reverse Current IGSS.
This internal input resistance can be calculated at different VGS :
RIN=|VGS/IGSS|
As IGSS increases with temperature, RIN will decrease.

25. JFET Input Resistance Example 1:
Calculate RIN if IGSS=-2nA and VGS=-20V
Solution:
RIN=|VGS/IGSS|=|-20/-2n|=10G

26. JFET Biasing Circuit
Just as we learned that the bi-polar junction transistor must be biased for proper operation, the JFET also must be biased for operation.
Let’s look at some of the methods for biasing JFETs.
In most cases the ideal Q-point will be the middle of the transfer characteristic curve which is about half of the IDSS.
4 types of bias method are self-bias, gate-bias, voltage-divider bias and current-source bias.

27. JFET Biasing- Self bias
Self-bias is the most common type of biasing method for JFETs.
Notice there is no voltage applied to the gate, VG=0V.
However, the voltage from gate to source (VGS) will be negative for n channel and positive for p channel to keep the junction reverse biased.
Fig 7-16 n channel

28. JFET Biasing- Self bias
Uses a source resistor to help reverse bias JFET gate. The gate is returned to ground via RG, and RS has been added to source circuit.
This voltage can be determined using the formulas below.
ID = IS for all JFET circuits. VG=0 and VS=IDRS.
VGS = VG - VS
(n channel) VGS = 0-IDRS
=-IDRS
(p channel) VGS = 0-(-IDRS )
=IDRS

29. JFET Biasing – self bias
Keep in mind that analysis of p-channel is the same as n-channel except for opposite polarity voltages.
The drain voltage with respect to ground is:
VD = VDD – IDRD
Since VS = IDRS, VDS is:
VDS = VD – VS
= VDD – ID(RD+RS)

31. JFET Biasing-self bias
Setting the Q-point requires us to determine a value of RS that will give us the desired ID and VGS. The formula below shows the relationship.
RS = | VGS/ID |
For a desired value of VGS, ID can be determined from the either the transfer characteristic curve or more practically from the formula below. The data sheet provides the IDSS and VGS(off).
ID = IDSS(1 - VGS/VGS(off))2
Fig. 7-16a n channel JFET
Fig 7-12

33. JFET Midpoint Biasing-self bias-formula method
Midpoint biasing- desirable to bias a JFET near the midpoint of its transfer characteristic curve where ID =IDSS / 2. ID is approximately one-half of IDSS when:
VGS  VGS(off)/3.4
Fig. 7-16a n channel JFET
Fig 7-12 n channel curve

34. JFET Midpoint Biasing-self bias-formula method
The value of RS needed to establish VGS can be determined by the relationship below.
RS = | VGS/ID |
To set the drain voltage at midpoint (VD=VDD/2), select a value of RD to produce the desired voltage drop.
The value of RD needed can be determined by taking half of VDD and dividing it by ID.
RD = (VDD/2)/ID
Fig. 7-16a n channel JFET
Fig 7-12 n channel curve

36. JFET Biasing- self-bias
Remember the purpose of biasing is to set a dc operating point (Q-point). In a self-biasing type JFET circuit, the Q-point is determined by the given parameters of the JFET itself and values of RS and RD. Setting it at midpoint on the drain curve is most common.
One thing not mentioned in the discussion is RG. It’s value is arbitrary large to prevent loading on the driving stage in a cascaded amplifier arrangement.
Fig. 7-16a n channel JFET

37. JFET Midpoint Biasing-self bias-graphical method
The transfer characteristic curve along with other parameters can be used to determine the mid-point bias Q-point of a self-biased JFET circuit.
First, establish dc load line by calculating VGS.
VGS = -IDRS for ID=0 and ID=IDSS
With 2 points (ID=0 and ID=IDSS), draw dc load line on the transfer characteristic curve.
The point where the two lines intersect gives us the ID and VGS (Q-point) needed for mid-point bias. Note that load line extends from VGS(off)(ID= 0A) to VP(ID = IDSS)
Fig 7-21 JFET self bias dc load line

38. JFET Midpoint Biasing-self bias-graphical method

40. JFET Biasing- voltage divider bias-formula
Voltage-divider bias can also be used to bias a JFET. R1 and R2 are used to keep the gate-source junction in reverse bias. Operation is no different from self-bias. Determining VGS for a JFET voltage-divider circuit with givenVD can be calculated with the formulas below.
Source voltage,VS = IDRS
Gate voltage, VG =(R2/R1+R2)VDD
Gate-to-source voltage.VGS=VG –VS
Source voltage, VS = VG - VGS
Fig 7-23 n channel voltage divider

41. JFET Biasing- voltage-divider bias - formula
VS must be more +ve than VG in order to keep VGS reverse-biased (-ve value).
Drain current, ID = (VDD – VD)/RD or
Since ID=IS, then ID=VS/RS

42. **MAKE SURE DELETE SLIDE NI UTK MSUK DLM COURSE FILE**

43. JFET Biasing-voltage-divider bias-graphical
In using the transfer characteristic curve to determine the approximate Q-point we must establish the 2 points for the load line.
1st step draw dc load line:
The first point is ID = 0 and VGS =VG.
VS=IDRS=(0)RS=0V
VGS=VG-VS=VG-0=VG
The 2nd point is for VGS=0,
ID=(VG-VGS) / RS = VG / RS
ID=VG / RS and VGS=0.
Fig load line

44. Dc load line for JFET with voltage-divider bias
The point at which the load line intersect with transfer characteristic curve is Q-point.
Dc load line for JFET with voltage-divider bias

47. JFET Biasing – Current Source Bias
Current source bias  provides high Q-point stability by making value of ID independently of JFET.
From figure, JFET drain current equals BJT collector current. IDQ = IC
In this circuit, a BJT acts as the constant-current source because its emitter current is essentially constant if
A FET can also be used as a constant current source.

48. JFET Biasing- Current source bias
Advantage: provide the most stable Q-point value of ID.
Disadvantage: circuit complexity makes it undesirable for most applications.

50. JFET Biasing
Transfer characteristics can vary for JFETs of the same type. This would adversely affect the Q-point for self-bias analysis. Q-point is much more stable using voltage-divider bias and current source bias.

51. The Ohmic Region The slope of the characteristic curve
in the ohmic region is the dc drain-to-source conductance GDS of the JFET.
Thus, the dc drain-to-source resistance is given by

52. The JFET as a Variable Resistance
A JFET can be biased in either the active region or the ohmic region.
JFETs are often biased in the ohmic region for use as a voltage controlled
variable resistor.
The control voltage is VGS, and it determines the resistance by varying the Q-point.

53. The JFET as a Variable Resistance
To bias a JFET in the ohmic region, the dc load line must intersect the characteristic curve in the ohmic region.
Thus, to allows VDS to control RDS, the dc saturation current ID(sat), is set much less than IDSS so that the load line intersects most of the characteristic curves in the ohmic region.

54. The JFET as a Variable Resistance
Figure shows the operating region expanded with three Q-points shown (Q0, Q1, and Q2), depending on VGS.
As you move along the load line in the ohmic region, the value of RDS varies as the Q-point falls successively on curves with different slopes.
The Q-point is moved along the load line by varying

55. The JFET as a Variable Resistance
As this happens, the slope of each successive curve is less than the previous one.
A decrease in slope corresponds to less ID and more VDS, which implies an increase in RDS.
This change in resistance can be exploited in a number of applications where voltage control of a resistance is useful.
***RDS is the DC drain to source resistance
Q0: ID= 0.270mA, VDS=0.23V
Q1: ID=0.250mA, VDS=0.33V
Q2: ID=0.230mA, VDS=0.44V
Q3: ID=0.210mA, VDS=0.56V

56. The JFET as a Variable Resistance

57. MOSFET
The metal oxide semiconductor field effect transistor (MOSFET) is the second category of FETs. The difference is that there no pn junction structure instead gate of MOSFET is insulated from the channel by silicon dioxide layer. MOSFETs are static sensitive devices and must be handled by appropriate means.
There are depletion MOSFETs (D-MOSFET) and enhancement MOSFETs (E-MOSFET). Note the difference in construction. The E-MOSFET has no structural channel.
Fig 7-29 D-MOSFET construction
Fig 7-32 E-MOSFET construction

58. D-MOSFET
The D-MOSFET can be operated in depletion or enhancement modes. To be operated in depletion mode, a negative gate-to-source voltage is applied. With negative gate voltage, negative charges on the gate repel electrons from channel, leaving +ve ions in their place. N-channel is depleted of some electron, thus decreasing channel conductivity.
Fig 7-30a depletion mode
Fig 7-31 DMOSFET schem. symbols

59. D-MOSFET
To be operated in the enhancement mode the gate-to-source is made more positive, attracting more electrons into the channel for better current flow and thus enhancing the channel conductivity.
Remember we are using n channel MOSFETs for discussion purposes. For p channel MOSFETs, polarities would change.
Fig 7-30b enhancement mode

60. E-MOSFET
The E-MOSFET or enhancement MOSFET can operate in only the enhancement mode. With a positive voltage above a threshold value on the gate, an induced channel of thin layer of –ve charges is created.
The conductivity of channel is enhanced by increase VGS and thus pulling more electrons into channel area.
Fig 7-32 n channel EMOSFET
Fig 7-33 EMOSFET schem. symbols

61. POWER MOSFET
The lateral double diffused MOSFET (LDMOSFET) and the V-groove MOSFET (VMOSFET) are specifically designed for high power applications.
Fig 7-35 and 36 LD and V MOSFETs
Fig 7-38 dual gate schem symbol
LDMOSFET
VMOSFET

62. POWER MOSFET
Dual gate MOSFETs have two gates which helps control unwanted capacitive effects at high frequencies.

63. MOSFET Characteristics and Parameters
Since most of the characteristics and parameters of MOSFETs are the same as JFETs we will cover only the key differences.

64. D-MOSFET Characteristics and Parameters
The D-MOSFET operate in either +ve or –ve gate voltages. The point on the curves where VGS=0 corresponds to IDSS. The point where ID=0 corresponds to VGS(off). As with JFET, VGS(off)=-VP.
The equation to find drain current also the same as JFET:
ID = IDSS(1 - VGS/VGS(off) )2
Fig 7-13a & b n & p channel DMOSFET
Remember n and p channel polarity differences.

65. Example 7-13 For a certain D-MOSFET, IDSS=10mA and VGS(off)=-8V.
Is this n-channel or a p-channel?
Calculate ID at VGS=-3V.
Calculate ID at VGS=+3V.
Solution:
The device has a –ve VGS(off), this is an n-channel MOSFET.
ID=IDSS(1-VGS/VGS(off))2=(10mA)(1- (-3/-8))2 =3.91mA
ID=(10mA)(1- (+3/-8))2=18.9mA

66. E-MOSFET Characteristics and Parameters
The E-MOSFET for all practical purposes does not conduct until VGS reaches the threshold voltage (VGS(th)). ID when conducting can be determined by the formulas below. The constant K must first be determined from data sheet by taking ID(on) at any given value of VGS on a particular MOSFET.
Fig 7-40 a n channel curve
K = ID(on) /(VGS - VGS(th))2
ID = K(VGS - VGS(th))2

67. MOSFET Biasing- zero bias
The three ways to bias a MOSFET are zero-bias, voltage-divider bias, and drain-feedback bias.
For D-MOSFET zero biasing as the name implies has no applied bias voltage to the gate. The input voltage swings it into depletion and enhancement mode.
Fig 7-42 a & b zero bias

68. Zero bias Since VGS=0 and ID=IDSS, the drain-to-source voltage is:
VDS = VDD – IDSSRD
The purpose of RG is to accommodate ac signal input by isolating it from ground as shown in figure (b) above. Since there is no dc gate current, RG does not affect the zero gate-to-source bias.

69. MOSFET Biasing- voltage divider bias
For E-MOSFETs zero biasing cannot be used. Voltage-divider bias must be used to set the VGS greater than the threshold voltage (VGS(th)). ID can be determined as follows. To determine VGS, normal voltage divider methods can be used. The following formula can be applied.
VGS = (R2 / (R1+R2))VDD
VDS = VDD - IDRD
K = ID(on)/(VGS - VGS(th))2
ID = K(VGS -VGS(th))2
VDS can be determined by application of Ohm’s law and Kirchhoff’s voltage law to the drain circuit.
Fig 7-44a Voltage-divider EMOSFET

70. Example 7-16
Determine VGS and VDS for E-MOSFET circuit below. Assume MOSFET has minimum values of ID(on)=200mA at VGS=4V and VGS(th)=2V.

71. Solution example 7-16

72. MOSFET Biasing- drain feedback bias
With drain-feedback bias there is no voltage drop across RG making VGS = VDS. With VGS given determining ID can be accomplished by the formula below.
ID = (VDD – VDS)/RD
Fig 7-44b drain-feedback

73. Troubleshooting
As always, having a thorough knowledge of the devices makes for easier troubleshooting circuits utilizing them. We will discuss some the common faults associated with FET circuits. Experience in troubleshooting is the best teacher having basic theoretical knowledge is extremely helpful.

74. Troubleshooting
If VD = VDD in a self-biased JFET circuit it could be one of several opens. It is a clear indication of no drain current. Use of senses to check for obvious failures the first and easiest step. Replace the FET only if associated components are known to be good.
If VD is less than normal in a self-biased JFET circuit an open in the gate circuit is more than likely the problem. The low drain voltage would be indicative of more drain current flowing than normal.
Fig 7-47a & b self-biased symptoms

75. Troubleshooting
In a zero-biased D-MOSFET or drain-feedback biased E-MOSFET an open in the gate circuit is more difficult to detect. It may seem to be biased properly with dc voltages but will fail to work properly when an ac signal is applied.
Fig 7-48a & b DMOSFET faults

76. Troubleshooting
With a voltage-divider biased E-MOSFET circuit faults are more easily detected. With an open R1 there is no drain current, so the VD = VDD. With an open R2 full VDD is applied to the gate turning it on fully. VD = 0
Fig 7-49 EMOSFET volt.divider faults

77. Summary JFETs are unipolar devices.
JFETs have three terminals: Source, Gate, and Drain.
JFETs have a high input resistance since the gate-source junction is reverse biased.
Unwanted capacitance associated with FETs can be dealt with by using dual gate type FETs.
IDSS for all FETs is the maximum amount of current flow in the drain circuit when VGS is 0V.
All FETs must be biased for proper operation. Midpoint is most common for use in amplifiers.

78. Summary
MOSFETs differ in construction in that the gate is insulated from the channel.
D-MOSFETs can operate in both depletion and enhancement modes. E-MOSFETs can only operate in the enhancement mode.
E-MOSFETs have no physical channel. A channel is induced with VGS greater than VGS(th).
E-MOSFETs have no IDSS parameter.
There are special MOSFET designs for high power applications.