1. Intro & ISA.1 1/14 Instruction Set Architecture (ISA) (Ch: 2.1- 2.7, 2.10 4 th ed) Instructions: Language of the Computer Dr. Khaled El-Ayat

2. Intro & ISA.2 Instructions = Language of the Machine Instruction: words of machine’s language Instruction set: instructions – CPU vocabulary Chapter overview: –difference in design principles of RISC & CISC –other instruction set architectures –MIPS instruction set architecture instruction type instruction format addressing modes No. of registers 1/14

3. Intro & ISA.3 1/14 RISC vs CISC RISC -- Reduced Instruction Set Computer -- philosophy –fixed instruction length –load/store architecture all operands of ALU instructions must be in registers –limited addressing modes –limited operations Implies –fewer instructions –larger register file –longer program –good for pipelining –simpler control CISC: Complex Instruction Set Computer

4. Intro & ISA.4 1/14 Characteristics of some CISC & RISC CPUs

5. Intro & ISA.5 1/14 CISC Ex: 80x86 Registers 031 GPR 0EAX GPR 3EBX GPR 1ECX GPR 2EDX GPR 6ESI Code segment pointer CS Stack segment pointer (top of stack) SS Data segment pointer 0 DS Data segment pointer1 ES Data segment pointer2 FS Data segment pointer3 GS GPR 7EDI GPR 5EBP GPR 4ESP EIPInstruction pointer (PC) EFLAGSCondition codes Name Use

6. Intro & ISA.6 1/14 CISC Ex: x86 Instructions have Variable lengths! Variability is an issue, but is solved by MicroArchitecture e.g. Pentium II, III, IV JE JE EIP + displacement Offset CALL MOV EBX, [EDI + 45] PUSH PUSH ESI ADD w ADD EAX, #6765 Reg 448 6 8 32 53 413 Immediate Condition MOV 1 w 1 d 88 TEST EDX, #42 718 32 TEST Postbyte Immediate w Reg f. e. d. c. b. a. CALL Displacement r-m postbyte Displacement

7. Intro & ISA.7 1/14 Examples of Instruction Format Widths Variable: Fixed: Hybrid: … … X86, VAX,. MIPS, Sparc, PowerPC IBM 360/370, MIPS16, TMS320C54

8. Intro & ISA.8 1/14 Instruction Formats If code size is most important, use variable length instructions If performance is most important, use fixed length instructions Recent embedded machines (ARM, MIPS) added optional mode to execute subset of 16-bit wide instructions (Thumb, MIPS16); per procedure decide performance or density Some architectures actually exploring on-the-fly decompression for more density.

9. Intro & ISA.9 1/14 Instruction Set Architecture: What Must be Specified? Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Next Instruction Instruction Format or Encoding –how is it decoded? Location of operands and result –where other than memory? –how many explicit operands? –how are memory operands located? –which can or cannot be in memory? Data type and Size Operations –what are supported Successor instruction –jumps, conditions, branches –fetch-decode-execute is implicit!

10. Intro & ISA.10 1/14 Typical Operations Data Movement Load (from memory) Store (to memory) memory-to-memory move register-to-register move input (from I/O device) output (to I/O device) push, pop (to/from stack) Arithmetic integer (binary + decimal) or FP Add, Subtract, Multiply, Divide Logical not, and, or, set, clear Shift shift left/right, rotate left/right Control (Jump/Branch) unconditional, conditional Subroutine Linkage call, return Interrupt trap, return Synchronization test & set (atomic r-m-w) String search, translate Graphics (MMX) parallel subword ops (4 16bit add)

11. Intro & ISA.11 1/14 Basic ISA Classes Accumulator (1 register): 1 address add A acc  acc + mem[A] 1+x address addx A acc  acc + mem[A + x] Stack: 0 address add tos  tos + next General Purpose Register : 2 address add A B EA[A]  EA[A] + EA[B] 3 address add A B C EA[A]  [B] + EA[C] Load/Store: 3 address add Ra Rb Rc Ra  Rb + Rc load Ra Rb Ra  mem[Rb] store Ra Rb mem[Rb]  Ra Most real machines are hybrids of these:

12. Intro & ISA.12 1/14 General Purpose Registers Dominate °1975-2000 all machines use general purpose registers °Advantages of registers registers are faster than memory registers are easier for a compiler to use - e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack registers can hold variables -memory traffic is reduced, so program is sped up (since registers are faster than memory) - code density improves (since register named with fewer bits than memory location)

13. Intro & ISA.13 1/14 MIPS R3000 Instruction Set Architecture: Registers Registers--32 general purpose registers –$zero (0) : 0 3 special purpose registers PC: program counter Hi, Lo for multiply and divide Word length=32 bits In memory: byte addressable

14. Intro & ISA.14 1/14 MIPS ISA: Instruction Categories Arithmetic & logic (AL) add $s1, $s2, $s3# $s1  $s2 + $s3 sub $s1, $s2, $s3# $s1  $s2 - $s3 –each AL inst. has exactly 3 operands all in registers Load/store -- data transfer instruction lw $s1, x($s2)# $s1 = memory [$s2+x] sw $s1, x($s2)# memory[$s2+x]=$s1 Jump & branch beq $s2, $s3, L1#branch to (PC)+L1 when ($s2) = ($s3) bne $s2, $s3, L1#branch to (PC)+L1 when ($s2) ($s3) slt $s2, $s3, $s4#set on less than, $s2=1 if ($s3) < ($s4) j L1# goto L1 floating point, memory management, etc.(will not be covered)

15. Intro & ISA.15 1/14 MIPS Instruction Formats Instruction format: layout of the instruction 3 types of formats: R-type (regular) I-type (Immediate) J-type (Jump) R-type: 6 fields –op: operation code (6 bits) –rs: 1st register source operand (5) –rt: 2nd register source operand (5) –rd: register destination (5) –sa: shift amount (5) –function: select the variant of operation in op field (6) OP rs rt rd sa funct OP rs rt immediate OP Target

16. Intro & ISA.16 1/14 Instruction Format::R-Type Example: add $8, $17, $18 OP=00, FUNC=40 Other R-type instructions sub $1, $2, $3 slt $1, $2, $3 jr $ra(31)#jump register, for returning to the calling procedure OP rs rt rd sa funct

17. Intro & ISA.17 1/14 Instruction Format/I-type 4 fields, 32 bits Immediate (address ) field: 16 bits, holds a constant Example: load word -- lw $s1, 50($s2) lw $s1, 48($s2)# $s1 = memory [$s2+48] Other I-type inst. add immediate -- addi $8, $9, 100 branch on equal -- beq $1, $2, 25: goto (PC+4)+100 if $1=$2

18. Intro & ISA.18 1/14 Instruction Format/J-Type 2 fields: 32 bits op: 6 bits address field: 26 bits Example: j 200# go to location f(4*200) Other J type inst.: jal 200 # jump & link, goto location f(4*200) $31(ra)= PC + 4

19. Intro & ISA.19 1/14 j label#go to label Jump Instruction Basics Instruction Format (J Format): op 26-bit address PC 4 32 26 32 00

20. Intro & ISA.20 1/14 MIPS Addressing Modes Register addressing –operand is in a register e.g. add $8, $19, $18 Base or displacement addressing –operand: at memory location reg. + constant (base) e.g. lw $8, 200($19) Immediate addressing –operand: constant, in inst. e.g. addi $8, $8, 4 PC-relative addressing –address = (PC) + constant in inst. e.g., bne $8, $21, Exit Pseudodirect addressing: jump address = PC(31-28) (concatenated with) jump constant*4

21. Intro & ISA.21 1/14 MIPS Addressing Mode Summary

22. Intro & ISA.22 1/14 MIPS Organization So Far Processor Memory 32 bits 2 30 words read/write addr read data write data word address (binary) 0…0000 0…0100 0…1000 0…1100 1…1100 Register File src1 addr src2 addr dst addr write data 32 bits src1 data src2 data 32 registers ($zero - $ra) 32 5 5 5 PC ALU 32 0123 7654 byte address (big Endian) Fetch PC = PC+4 DecodeExec Add 32 4 Add 32 branch offset

23. Intro & ISA.23 1/14 bne $s0, $s1, Lbl#go to Lbl if $s0  $s1 beq $s0, $s1, Lbl#go to Lbl if $s0=$s1 –Ex: if (i==j) h = i + j; bne $s0, $s1, Lbl1 add $s3, $s0, $s1 Lbl1:... MIPS Conditional Branch Instructions Instruction Format (I format): op rs rt 16 bit offset Target Address = PC +4 + (offset * 4)

24. Intro & ISA.24 1/14 Fr other type of branch conditions Use slt Set on less than instruction: slt $t0, $s0, $s1 # if $s0 < $s1 then # $t0 = 1else # $t0 = 0 Instruction format (R format): 2 More Branch Instructions op rs rt rd funct

25. Intro & ISA.25 1/14 More Branch Instructions, Con’t Can use slt, beq, bne, and the value 0 in register $zero to create other conditions –less than blt $s1, $s2, Label –less than or equal to ble $s1, $s2, Label –greater than bgt $s1, $s2, Label –great than or equal to bge $s1, $s2, Label slt $at, $s1, $s2#$at set to 1 if bne $at, $zero, Label# $s1 < $s2 Such branches are included in the instruction set as pseudo instructions - recognized (and expanded) by the assembler

26. Intro & ISA.26 1/14 addi$sp, $sp, 4#$sp = $sp + 4 slti $t0, $s2, 15#$t0 = 1 if $s2<15 Machine format (I format): MIPS Immediate Instructions op rs rt 16 bit immediate I format Small constants are used often in typical code Constant kept inside the instruction –Immediate format limits values to the range +2 15 –1 to -2 15

27. Intro & ISA.27 1/14 To load a 32 bit constant into a register, we use two instructions a new "load upper immediate" instruction lui $t0, 1010101010101010 Then must get the lower order bits right, use ori $t0, $t0, 1010101010101010 How About Larger Constants? 16 0 8 1010101010101010 1010101010101010 00000000000000001010101010101010 0000000000000000 1010101010101010

28. Intro & ISA.28 1/14 MIPS ISA So Far CategoryInstrOp CodeExampleMeaning Arithmetic (R & I format) add0 and 32add $s1, $s2, $s3$s1 = $s2 + $s3 subtract0 and 34sub $s1, $s2, $s3$s1 = $s2 - $s3 add immediate8addi $s1, $s2, 6$s1 = $s2 + 6 or immediate13ori $s1, $s2, 6$s1 = $s2 v 6 Data Transfer (I format) load word35lw $s1, 24($s2)$s1 = Memory($s2+24) store word43sw $s1, 24($s2)Memory($s2+24) = $s1 load byte32lb $s1, 25($s2)$s1 = Memory($s2+25) store byte40sb $s1, 25($s2)Memory($s2+25) = $s1 load upper imm15lui $s1, 6$s1 = 6 * 2 16 Cond. Branch (I & R format) br on equal4beq $s1, $s2, Lif ($s1==$s2) go to L br on not equal5bne $s1, $s2, Lif ($s1 !=$s2) go to L set on less than0 and 42slt $s1, $s2, $s3if ($s2<$s3) $s1=1 else $s1=0 set on less than immediate 10slti $s1, $s2, 6if ($s2<6) $s1=1 else $s1=0 Uncond. Jump (J & R format) jump2j 2500go to 10000 jump register0 and 8jr $t1go to $t1 jump and link3jal 2500go to 10000; $ra=PC+4

29. Intro & ISA.29 1/14 MIPS arithmetic instructions InstructionExampleMeaningComments add add $1,$2,$3$1 = $2 + $33 operands; exception possible subtractsub $1,$2,$3$1 = $2 – $33 operands; exception possible add immediateaddi $1,$2,100$1 = $2 + 100+ constant; exception possible add unsignedaddu $1,$2,$3$1 = $2 + $33 operands; no exceptions subtract unsignedsubu $1,$2,$3$1 = $2 – $33 operands; no exceptions add imm. unsign.addiu $1,$2,100$1 = $2 + 100+ constant; no exceptions multiply mult $2,$3Hi, Lo = $2 x $364-bit signed product multiply unsignedmultu$2,$3Hi, Lo = $2 x $364-bit unsigned product divide div $2,$3Lo = $2 ÷ $3,Lo = quotient, Hi = remainder Hi = $2 mod $3 divide unsigned divu $2,$3Lo = $2 ÷ $3,Unsigned quotient & remainder Hi = $2 mod $3 Move from Himfhi $1$1 = HiUsed to get copy of Hi Move from Lomflo $1$1 = LoUsed to get copy of Lo

30. Intro & ISA.30 1/14 MIPS logical instructions InstructionExampleMeaningComment and and $1,$2,$3$1 = $2 & $33 reg. operands; Logical AND oror $1,$2,$3$1 = $2 | $33 reg. operands; Logical OR xorxor $1,$2,$3$1 = $2  $33 reg. operands; Logical XOR nornor $1,$2,$3$1 = ~($2 |$3)3 reg. operands; Logical NOR and immediateandi $1,$2,10$1 = $2 & 10Logical AND reg, constant or immediateori $1,$2,10$1 = $2 | 10Logical OR reg, constant xor immediate xori $1, $2,10 $1 = ~$2 &~10Logical XOR reg, constant shift left logicalsll $1,$2,10$1 = $2 << 10Shift left by constant shift right logicalsrl $1,$2,10$1 = $2 >> 10Shift right by constant shift right arithm.sra $1,$2,10$1 = $2 >> 10Shift right (sign extend) shift left logicalsllv $1,$2,$3$1 = $2 << $3 Shift left by variable shift right logicalsrlv $1,$2, $3 $1 = $2 >> $3 Shift right by variable shift right arithm.srav $1,$2, $3 $1 = $2 >> $3 Shift right arith. by variable

31. Intro & ISA.31 1/14 MIPS data transfer instructions InstructionComment SW 500(S4), S3Store word SH 502(S2), S3Store half SB 41(S3), S2Store byte LW S1, 30(S2)Load word LH S1, 40(S3)Load halfword LHU S1, 40(S3)Load halfword unsigned (no sign extension) LB S1, 40(S3)Load byte LBU S1, 40(S3)Load byte unsigned (no sign extension) LUI S5, 40Load Upper Immediate (16 bits shifted left by 16) Why need LUI? 0000 … 0000 LUI S5 S5

32. Intro & ISA.32 1/14 How shift instructions are implemented Two kinds: logical-- value shifted in is always "0" arithmetic-- on right shifts, sign extend No arithmetic Left Shift – Overflow result msblsb"0" msblsb Note: these are single bit shifts. A given instruction might request 0 to 32 bits to be shifted!

33. Intro & ISA.33 1/14 When does MIPS sign extend? When value is sign extended, copy upper bit to full value: Examples of sign extending 8 bits to 16 bits: 00001010  00000000 00001010 10001100  11111111 10001100 When is an immediate operand sign extended? –Arithmetic instructions (add, sub, etc.) always sign extend immediates –Logical instructions do not sign extend immediates (They are zero extended) –Load/Store address computations always sign extend immediates Multiply/Divide have no immediate operands however: –“unsigned”  treat operands as unsigned The data loaded by the instructions lb and lh are extended as follows (“unsigned”  don’t extend ) : –lbu, lhu are zero extended –lb, lh are sign extended

34. Intro & ISA.34 1/14 MIPS Compare and Branch Summary Compare and Branch –BEQ rs, rt, offset if R[rs] == R[rt] then PC-relative branch –BNE rs, rt, offset <> Compare to zero and Branch –BLEZ rs, offset if R[rs] <= 0 then PC-relative branch –BGTZ rs, offset > –BLT < –BGEZ >= –BLTZAL rs, offset if R[rs] < 0 then branch and link (into R 31) –BGEZAL >=! Almost all comparisons are against zero!

35. Intro & ISA.35 1/14 MIPS jump, branch, compare instructions InstructionExampleMeaning branch on equalbeq $1,$2,25if ($1 == $2) go to PC+4+100 Equal test; PC relative branch. Note: Offset field = 25 branch on not eq.bne $1,$2,25if ($1!= $2) go to PC+4+100 Not equal test; PC relative Note: Offset field = 25 set on less thanslt $1,$2,$3if ($2 < $3) $1=1; else $1=0 Compare less than; 2’s comp. set less than imm.slti $1,$2,100if ($2 < 100) $1=1; else $1=0 Compare < constant; 2’s comp. set less than uns.sltu $1,$2,$3if ($2 < $3) $1=1; else $1=0 Compare less than; natural numbers set l. t. imm. uns.sltiu $1,$2,100if ($2 < 100) $1=1; else $1=0 Compare < constant; natural numbers jumpj 2500go to 10000 Jump to target address Note: jump field = 2500 jump registerjr $31go to $31 For switch, procedure return jump and linkjal 2500$31 = PC + 4; go to 10000 For procedure call. Note: jump field = 2500

36. Intro & ISA.36 1/14 Subroutine Calls & Stacks Stacking of Subroutine Calls & Returns and Environments: A: CALL B CALL C C: RET B: A AB ABC AB A Some machines provide a memory stack as part of the architecture (e.g., VAX) Sometimes stacks are implemented via software convention (e.g., MIPS) Some machines provide stack support in hardware (Embedded processor)

37. Intro & ISA.37 1/14 0zero constant 0 1atreserved for assembler 2v0expression evaluation & 3v1function results 4a0arguments 5a1 6a2 7a3 8t0temporary: caller saves...(callee can clobber) 15t7 MIPS: Software conventions for Registers 16s0callee saves... (callee must save) 23s7 24t8 temporary (cont’d) 25t9 26k0reserved for OS kernel 27k1 28gpPointer to global area 29spStack pointer 30fpframe pointer 31raReturn Address (HW)

38. Intro & ISA.38 1/14 Summary of MIPS I ISA 32-bit fixed format inst (3 instruction formats / types) 32 32-bit GPR (R0 contains zero) and 32 FP registers (and HI LO) – partitioned by software convention 3-address, reg-reg arithmetic instr. Single address mode for load/store: base+displacement 16-bit immediate plus LUI Simple branch conditions – compare against zero or two registers for =,  – no integer condition codes