1. Project Final Semester A Presentation Implementing a compressor in software and decompression in hardware Presents by - Schreiber Beeri Yavich Alon Guided by – Porian Moshe 03.2011

2. Reminder 142 ❤ Compressed data (Wireless) Gym 132 ❤ 170 ❤ 79 ❤ 130 ❤ 127 ❤ Gym Control Room

3. TOP ARCHITECTURE

4. VGA Display Host Matlab UART RX UART TX Message Decoder RAM MUX Message Encoder RAM DEC Display Controller RunLen Decoder CRC IS42S16400 SDRAM SDRAM Controller Arbiter Mem Write Mem Read REGISTERS Packet TX Packet RX Ext. Clk Global Nets Ext. Reset Sync Resets FPGA – Cyclone II TX RX VESA 115,200KBit/sec 800x600 Done Implemented, not integrated Update Required Not Implemented Clocks

5. MICRO ARCHITECTURE

6. DATA Addr DATA COLOR DATA Data& Valid Message Decoder RAM DEC Mem Write Arbiter SDRAM Controller Mem Read RunLen Decoder REGISTERS VGA Display TX PACK Global Nets Sync Resets SDARM UART Matlab UART RXP RAM Controller Display Controller FIFO (dual clock) FIFO (dual clock) UART TXP REG Controller Addr REG TYPE REG CheckSum Len REG UART RXD UART TXD from UART TX VALID DATA REG CRC STATUS CRC_ERR FROM MSG_DEC MP REGS RESET Status REQ VALID CRC_ERR DATA WREN WR_addr RD_adress Type DATA REQ EN REQ ACK REQ Adress ACK VALID DATA RX_RDY to MEM READ RX_RDY from MEM READ DATA_RDY to MEM READ DATA_RDY from MEM READ REP VALID DATA COLOR COL_EN DATA RGB UART TXD to UART TX 50MHZ 40MHZ (VESA) 133MHZ (SDRAM) 1 bit 8 bits 10 bits 16 bits 22 bits Line legend Data & Control MSG_OK Num Pixels n_pix 40MHz CheckSum & Valid CRC Status FIFO FULL EMPTY DATA & Valid REQ Reset 40MHz

7. Global Nets New Implemented IPs

8. Global Nets Reset Filter New Implemented IPs

9. Global Nets Sync Reset Generator Sync Reset De-activation 50MHz 133MHz / 40MHz New Implemented IPs

10. Global Nets Wave New Implemented IPs

11. VESA Generator VESA Generator: Supports any kind of resolution and timing (Set by generic parameters) Inputs: R, G, B (Generic size for each) Frames sizes (Wraps the image) Handshake with data provider Outputs: R, G, B Hsync, Vsync, Blank signals Handshake with Data Provider New Implemented IPs

12. VESA Generator VESA Generator: Pinout RGB (from Data Provider) Frame Parameters Enables Handshake RGB Sync, Blank Handshake New Implemented IPs

13. VESA Generator VESA Generator: Pipeline, for supporting greater clock frequencies New Implemented IPs

14. VESA Generator VESA Generator: Pipeline, for supporting greater clock frequencies New Implemented IPs

15. VESA Test Bench Image Data Provider Image Collector This will be shown using VGA and DE2 board RGBRGB Frames Sizes Handshake RGBRGB VSync Enables HSync Blank Frame Image

16. VESA Test Bench Frame Output Examples

17. Maximum Current Project’s Frequency 163MHz. UART RX is the slowest component. Pin Signal route through FPGA Logic

18. Improvements done from last presentation UART Rx ◦ Data is being collected to Shift Register Message Packs: ◦ Data is being collected and transmitted using Shift Register. ◦ Maximum frequency improved from 150MHz to 180MHz

19. New Implemented Simulation Models VESA Image Generator ◦ Transmits an image from file, with different image’s parameters, and different frames sizes VESA Image Collector ◦ Collects transmitted images, and store them to file

20. Documentations Done: ◦ SDRAM Controller * ◦ UART RX, TX ◦ MessagePack + Checksum ◦ VESA ◦ Clocks and Resets Documentation Example: VESA

21. Conclusions 2 FF for every a synchronized input FPGA pin is essential, to prevent metastability from entering the system. Using Shift Register makes the design to work in greater clock frequency. Pipeline can improve performance. RTL view can teach a lot: RAM can be implemented in many ways, and only RTL can show what is the correct way.

22. Conclusions (Cont.) Synchronizing the reset negation to the clock’s rising edge is essential, to prevent metastability from entering the system.

23. Conclusions (Cont.) Organized working methods saves time: ◦ SVN – Difference between previous versions ◦ Code Review – Improves our knowledge ◦ Documentations – Causes to understand better what we are doing ◦ Comprehensive SIMULATIONS – It is much easier to find bugs in simulation than in the lab  S A V E S T I M E!!!

24. Schedule To do…DateNum. Theoretical self-instruction1.10 – 16.101 Run length algorithm implementation17.10 – 23.102 SDRAM Controller implementation24.10 – 30.103 Architecture definition31.10 – 15.114 Project Characterization presentation16.115 Full characterization of all blocks17-1.126 Implement UART RX-MP & TB2.12-8.127 Implement UART TX-MP & TB9-15.128 Prepare Mid. Presentation16-27.129 Done Partial Done

25. Schedule To do…DateNum. (1)Implement Display Controller & TB (2)Update Debouncer 11.1-26.110 Exams!!! Prepare documentation to existing models, end of semester presentation, and final semester A report 27.1-22.211 Present end of semester presentation23.212 Finish Generic RAM + TB1.413 Implement Register Bus + TB (According to Wishbone Standard) 1.514 Adjust SDRAM Model to our SDRAM7.515 Build TB for SDRAM14.516 Mid Presentation18.517 Implement SDRAM Rd/Wr Blocks24.518 Done Now

26. Schedule To do…DateNum. Implement Memory Arbiter block31.519 Implement Runlen Decoder + TB5.620 Build TB for the whole project10.621 Simulations & Debug26.622 Synthesis of all the whole project1.723 Upgrade GUI7.724 Final debug in lab & simulation27.725 Final Presentation15.826