1. Switch Logic
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2. What is a transistor? An MOS Transistor A Switch
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3. Switch Model of MOS Transistor
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4. NMOS and PMOS
NMOS transistor PMOS transistor
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5. The CMOS Inverter: A First Glance
out C L DD
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6. CMOS Inverter N Well V DD PMOS 2l Contacts Out In Metal 1 Polysilicon
NMOS
GND
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7. Two Inverters
Share power and ground
Abut cells
Connect in Metal
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8. CMOS Inverter First-Order DC AnalysisDD in 5
out R n p
VOL = 0
VOH = VDD
VM = f(Rn, Rp)
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9. CMOS Inverter: Transient ResponseDD DD t
pHL
= f(R on .C L )
= 0.69 R C R p V
out V
out C L C L R n V 5 V 5 V in in DD
(a) Low-to-high
(b) High-to-low
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10. Simulated VTC
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11. Inverter Chain In Out CL If CL is given:
How many stages are needed to minimize the delay?
How to size the inverters?
May need some additional constraints.
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12. Inverter Delay Minimum length devices, L=0.25mm
Assume that for WP = 2WN =2W
same pull-up and pull-down currents
approx. equal resistances RN = RP
approx. equal rise tpLH and fall tpHL delays
Analyze as an RC network 2W W
Delay (D):
tpHL = (ln 2) RNCL
tpLH = (ln 2) RPCL
Load for the next stage:
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13. Inverter with Load RW CL RW tp = k RWCL k is a constant, equal to 0.69
Delay RW CL RW
Load (CL)
tp = k RWCL
k is a constant, equal to 0.69
Assumptions: no load -> zero delay
Wunit = 1
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14. Inverter with Load CP = 2Cunit 2W W Cint CL CN = Cunit
Delay 2W W
Cint CL
Load
CN = Cunit
Delay = kRW(Cint + CL) = kRWCint + kRWCL = kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)
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15. Delay Formula Cint = gCgin with g  1 f = CL/Cgin - effective fanout
R = Runit/W ; Cint =WCunit
tp0 = 0.69RunitCunit
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16. Apply to Inverter Chain
Out CL 1 2 N
tp = tp1 + tp2 + …+ tpN
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17. Optimal Tapering for Given N
Delay equation has N - 1 unknowns, Cgin,2 – Cgin,N
Minimize the delay, find N - 1 partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
each stage has the same effective fanout (Cout/Cin)
each stage has the same delay
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18. Optimum Delay and Number of Stages
When each stage is sized by f and has same eff. fanout f:
Effective fanout of each stage:
Minimum path delay
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19. Example In
Out
CL= 8 C1 1 f f2 C1
CL/C1 has to be evenly distributed across N = 3 stages:
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20. Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
For g = 0, f = e, N = lnF
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21. Optimum Effective Fanout f
Optimum f for given process defined by g
fopt = 3.6
for g=1
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22. Buffer Design
N f tp
2 8 18
3 4 15 1 64 1 8 64 1 4 16 64 1 64
22.6
2.8 8
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