1. Chapter 0 - reVieW Combinational Logic Circuit, Combinational Logic Circuit, Propagation Delay, Propagation Delay, Programmable Logic. Programmable Logic. EKT 221 / 4 DIGITAL ELECTRONICS II

2. What have been discussed Design hierarchy –Top – down –Bottom – up CAD (Computer Aided Design) HDL (Hardware Description Language) Logic synthesis

3. Analysis Procedure Analysis –To determine the function of a circuit Derive Boolean equation Derive truth table

4. Analyze this logic diagram T1 T3 T2 T4 T5

5. Boolean Equation T1 =BC T2 =AB T3 =A+T1=A+BC T4 =T2 + D = AB + D T5 =AB+D F1 = (A+BC) + (AB + D) F2 = T5 = AB + D

6. Analyze this Binary Adder R1 R2 R3 C

7. Truth Table XYZCCR1R2R3S

8. XYZ 000 001 010 011 100 101 110 111CCR1R2R3S010000 010111 010111 100100 010111 100100 100100 101101

9. Logic Simulation A fast and accurate method of analyzing a combinational circuit Using simulator software Results : –Waveforms –A complete truth table –Part of a truth table

10. Logic Simulation How is the circuit described in the software ? –Schematics –HDL

11. Schematic for Binary Adder in Xilinx

12. Waveforms for Binary Adder

13. Simulation in Max Plus II

14. Waveforms in MaxPlus II

15. Point to ponder…. Why do we compare the simulation results vs the theoretical results?

16. Design Procedure Given : Specifications of the problem 1. Determine input & output 2. Derive truth table 3. Obtain Boolean equation (K-map) 4. Draw schematics 5. Verify design

17. Design of BCD to Excess – 3 Code Converter Specifications : Input in decimal numbers, 0 – 9, in binary form Output is excess – 3 code E.g –Decimal = 5 (101) –Excess – 3 code = 5 + 3 = 8 (1000)

18. BCD  Excess – 3 Step 1. –Input : 0 to 9, 4 – bit binary code  A, B, C, D –Output : 3 to 12, 4 – bit binary code  W, X, Y, Z

19. BCD  Excess – 3 Step 2 : Truth Table Dec 0 1 2 3 4 5 6 7 8 9ABCD0000 0001 0010 0011 0100 0101 0110 0111 1000 1001WXYZ0011 0100 0101 0110 0111 1000 1001 1010 1011 1100

20. BCD  Excess – 3 Step 3 : Boolean equation W = A + BC + BD W = A + BC + BD X = BC + BD + BCD X = BC + BD + BCD Y = CD + CD Y = CD + CD Z= D Z= D

21. BCD  Excess – 3 Step 4 : Schematic diagram

22. BCD  Excess – 3 Step 4 : Schematic diagram

23. BCD  Excess – 3 Step 5 : Verify that schematic diagram agrees with truth table

24. Design of BCD to 7 –segment decoder Specifications : Input in decimal numbers, 0 – 9, in binary form 7 Outputs – to display input number

25. 7 – segment Display

26. BCD to 7 –segment decoder Step 1 :

27. BCD to 7 – segment decoder Step 2 : Truth Table ABCD 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 All other inputs abcdefg1111110 0110000 1101101 1111001 0110011 1011011 1011111 1110000 1111111 1111011 0000000

28. Exercise A traffic light system has the following specifications for a part of its controller. There are 3 parallel lanes, each with its own red / green light. One of these lanes, the priority lane, is given priority for a green light over the other 2 lanes. On the other hand, an alternating scheme is used for the other 2 lanes, which are left and right lane. Design the circuit that determines which light is to be green at a particular time. The specifications for the controller are as follows :

29. Exercise Inputs : PS – Priority Lane Sensor ( car present = 1; car absent = 0 ) LS – Left Lane Sensor ( car present = 1; car absent = 0 ) RS – Right Lane Sensor ( car present = 1; car absent = 0 ) AS – Alternating Signal ( select left = 1; select right = 0 ) Outputs : PL – Priority Lane Light ( green = 1; red = 0 ) LL – Left Lane Light ( green = 1; red = 0 ) RL – Right Lane Light ( green = 1; red = 0 )

30. Exercise 1. If there is a car in the priority lane, PL = 1. 2. If there are no cars in the priority lane and the right lane, and there is a car in the left lane, LL = 1. 3. If there are no cars in the priority lane and in the left lane, and there is a car in the right lane, RL = 1. 4. If there is no car in the priority lane, there are cars in both the left and right lanes, and AS = 1, then LL = 1. 5. If there is no car in the priority lane, there are cars in both the left and right lanes, and AS = 0, then RL = 1. 6. If any PL, LL or RL is not specified to be 1 above, then it has value 0.

31. Chapter 0 Propagation Delay & Programmabe Logic

32. Propagation Delay Propagation delay is the time for a change on an input of a gate to propagate to the output. Delay is usually measured at the 50% point with respect to the H and L output voltage levels. High-to-low (t PHL ) and low-to-high (t PLH ) output signal changes may have different propagation delays. High-to-low (HL) and low-to-high (LH) transitions are defined with respect to the output, not the input. An HL input transition causes: –an LH output transition if the gate inverts and –an HL output transition if the gate does not invert.

33. Propagation Delay (continued) Propagation delays measured at the midpoint between the L and H values What is the expression for the t PHL delay for: –a string of n identical buffers? –a string of n identical inverters?

34. Propagation Delay Example Find t PHL, t PLH and t pd for the signals given IN (volts) OUT (volts) t (ns) 1.0 ns per division

35. Implementation Technology Programmable Implementation Technologies –Read-Only Memories, Programmable Logic Arrays, Programmable Array Logic Technology mapping to programmable logic devices

36. Why Programmable Logic? Facts: –It is most economical to produce an IC in large volumes –Many designs required only small volumes of ICs Need an IC that can be: –Produced in large volumes –Handle many designs required in small volumes A programmable logic part can be: – made in large volumes – programmed to implement large numbers of different low-volume designs

37. Programmable Logic - Additional Advantages Many programmable logic devices are field- programmable, i. e., can be programmed outside of the manufacturing environment Most programmable logic devices are erasable and reprogrammable. –Allows “updating” a device or correction of errors –Allows reuse the device for a different design - the ultimate in re-usability! –Ideal for course laboratories Programmable logic devices can be used to prototype design that will be implemented for sale in regular ICs. –Complete Intel Pentium designs were actually prototype with specialized systems based on large numbers of VLSI programmable devices!

38. Technology Characteristics Permanent - Cannot be erased and reprogrammed Mask programming FuseAntifuseReprogrammable –Volatile - Programming lost if chip power lost Single-bit storage element –Non-Volatile Erasable Electrically erasable Flash (as in Flash Memory) –Build lookup tables Storage elements (as in a memory) –Transistor Switching Control Stored charge on a floating transistor gate –Erasable –Electrically erasable –Flash (as in Flash Memory) Storage elements (as in a memory)

39. Programmable Configurations Read Only Memory (ROM) - a fixed array of AND gates and a programmable array of OR gates Programmable Array Logic (PAL)  - a programmable array of AND gates feeding a fixed array of OR gates. Programmable Logic Array (PLA) - a programmable array of AND gates feeding a programmable array of OR gates. Complex Programmable Logic Device (CPLD) /Field- Programmable Gate Array (FPGA) - complex enough to be called “architectures” - See VLSI Programmable Logic Devices reading supplement

40. The End Let each day of your day be a masterpiece, cause today might be your last day to do it…