1. RPC Trigger Software

2. Michał Pietrusiński Hardware setup VME Bit3 Controller Link Board 1Link Board 2Link Board 3Link Board 4 Trigger Board Pattern Unit VME-PCI SBS Interface TTCvi WinNT 4 RPC PCI-VME Ethernet TB equipped with embedded PC (EtLinux)

3. Michał Pietrusiński Applications aboot – command line utility to load Altera FPGAs interbs – simple command line utility to interact with JTAG boards Basic JTAG operations (TAP state, send/receive vectors of bits) Chip and board level operations – access to elements by its name: read/write specific chip registers execute JTAG instructions set/get state of specific pin/signal

4. Michał Pietrusiński interbs – example of usage suncms1:/usr/local/bin>interbs chain.bsc PAC:pt ALTERA:ap PAC:pac ALTERA:ac interbs>reset interbs>ss pt BYPASS interbs>ss ap BYPASS interbs>ss pac SAMPLE interbs>ss ac BYPASS interbs>sir sending sequence:11101001111111 received=10110001011000 interbs>sdr sending sequence: 00000000000000000000000000000000000000000000000000000000000000000000000 Received sequence: 00000000000000000000000000000000000000000000000000000000000000000101000 interbs>gs pac|BOUN_REG|sig|codeout3 o1 interbs>gs pac|BOUN_REG|sig|codeout4 o0 interbs>gs pac|BOUN_REG|sig|codeout5 o1 interbs>gs pac|BOUN_REG|sig|codeout6 o0 interbs>quit List of chips in the chain Set TAP to Reset state Prepare the program to execute given instructions in chips Send/rec sequence to instruction registers Send/rec sequence to data registers (length of chain is calcuated automaticaly) Print state of some signals: o1 - output high o0 – output low

5. Michał Pietrusiński Applications (cont’d) TTCcontr – Windows application that gives full control of TTCvi and TTCrx boards Supports older (TTCvi MK I) and latest (TTCvi MK II) versions of TTCvi Easy control of all TTCvi and TTCrx functions and settings User-defined sequences of B-Channel cycles stored in ini file Presettings (stored in ini file) - user can save current settings of TTCvi and TTCrx and apply theme later by clicking one button

6. Michał Pietrusiński TTC screenshot

7. Michał Pietrusiński Applications (cont’d) punit – visual Windows application to send test pulses using Pattern Unit (one word = 128 bits) edit scripts wtih signal definitions, macros, loops, etc. parse, programm device, run. tbcc (Test Bench Control Center) – visual application used to control RPC trigger prototypes during beam tests. Setting control registers. Histogramming

8. Michał Pietrusiński Beam-test software goals Hardware setup and control (FPGAs loading, setting control registers) Readout of boards, histogramming Intuitive GUI: software is to be used by non software experts Reusable, easy to modify High performance

9. Michał Pietrusiński Tbcc screenshot

10. Michał Pietrusiński Packages VME library Altera loading package JTAG primitives library (bscontr) JTAG layout library (bslayout) Test pulses generation library (punit) Histogramming package Internal Interface (II) package TTCvi package

11. Michał Pietrusiński Package dependencies

12. Michał Pietrusiński Boundary Scan package

13. Michał Pietrusiński Internal Interface package

14. Michał Pietrusiński II: VHDL and C++ VHDL and C++ code use common interface description files (iid) IID files describe: Registers, meanings of bits in registers, memory areas Their sizes Types of access IID files are directly included in C++ projects and automatically converted to VHDL using C++ preprocessor.

15. Michał Pietrusiński Tbcc screenshot II From lb_control.iid: IIDEC_COM_LINE( " item type item ID width num parent ID IIDEC_ITEM_BEG( VII_PAGE, PAGE_REGISTERS, 0, 0, PAGE_REGISTERS,... IIDEC_ITEM_CON( VII_WORD, WORD_IDENTIFIER, II_DATA_SIZE, 1, PAGE_REGISTERS,... IIDEC_ITEM_CON( VII_WORD, WORD_VERSION, II_DATA_SIZE, 1, PAGE_REGISTERS,... IIDEC_ITEM_CON( VII_VECT, VECT_STATUS, 0, 0, PAGE_REGISTERS,... IIDEC_ITEM_CON( VII_BITS, BITS_STATUS_CLOCK_SEL, CLOCK_SEL_SIZE, 1, VECT_STATUS,... IIDEC_ITEM_CON( VII_BITS, BITS_STATUS_TRG_SEL, TRG_SEL_SIZE, 1, VECT_STATUS,... IIDEC_ITEM_CON( VII_BITS, BITS_STATUS_PRETRG0_SEL, PRETRG_SEL_SIZE, 1, VECT_STATUS,... IIDEC_ITEM_CON( VII_BITS, BITS_STATUS_PRETRG1_SEL, PRETRG_SEL_SIZE, 1, VECT_STATUS,... IIDEC_ITEM_CON( VII_VECT, VECT_GOL, 0, 0, PAGE_REGISTERS,... IIDEC_ITEM_CON( VII_BITS, BITS_GOL_LASER, 1, 1, VECT_GOL,... IIDEC_ITEM_CON( VII_BITS, BITS_GOL_NEDGE, 1, 1, VECT_GOL,... IIDEC_ITEM_CON( VII_BITS, BITS_GOL_TX_ENA, 1, 1, VECT_GOL,... IIDEC_ITEM_CON( VII_BITS, BITS_GOL_TX_ERR, 1, 1, VECT_GOL,...

16. Michał Pietrusiński Histogramming package