1. W.Skulski APS April/2003 Eight-Channel Digital Pulse Processor And Universal Trigger Module. Wojtek Skulski, Frank Wolfs University of Rochester

2. W.Skulski APS April/2003 Outline Description of the DDC-8 and DDC-1. Response to scintillator pulses. Applications. PHOBOS @ RHIC. SuperBall+DwarfBall. Prospects: 32 channels in a single VME slot.

3. W.Skulski APS April/2003 Signal OUT 40 MHz * 10 bits JTAG connector micro processor FPGA ADC 40 MHz * 10 bits (8 channels) 16 bidirectional TTL lines + 1 in (fast parallel interface to XLM) Analog signal IN 8 channels with digital offset and gain control RS-232 Logic connectors NIM 16 lines IN, 8 lines OUT USB RAM 500 kB ECL clock IN (optional)

4. W.Skulski APS April/2003 Single channel 12-bit prototype, development and testing Input channel for waveform capture, up to 65 Msamples/s. Output reconstruction channel for development and diagnostic. The channel design to be used for the 12-bit multichannel board. Signal OUT JTAG connector USB processor connector FPGA Signal IN ADC 65 MHz * 12 bits Fast reconstruction DAC 65 MHz * 12 bits Variable gain amp

5. W.Skulski APS April/2003 ASC Nyquist filter ADC Sample rate processor Waveform memory Event rate processor Signal from preamplifier Clock Gain and offset control Optional external trigger analog digital Legend: ASC = Analog Signal Conditioning ADC = Analog to Digital Converter Trigger Pulse height and shape Individual trigger

6. W.Skulski APS April/2003 Analog section Digital section Correlation processor User-defined 16 I/O lines OR parallel interface Composite internal trigger Channel 1 Analog section Digital section Channel 2... Analog section Digital section Channel 8 Optional external trigger (one of the 16 NIM in lines) Internal triggers from channels 1…8 16*NIM in8*NIM out Analog section Digital section Channel OUT

7. W.Skulski APS April/2003 # of analog input channels 8. # of analog output channels 1. # of logic inputs NIM 16. # of logic outputs NIM 8. # of in/out lines TTL 16+1. Fast interfaces USB, parallel. Slow interfaces RS-232, SPI, I 2 C. Waveform memory 12  sec. Packaging NIM or standalone. Intermediate scale: SuperBall+DwarfBall. Medium scale: PHOBOS trigger. Small scale: table-top DPP systems, student research projects, DPP algorithm development. Eight-channel digital pulse processor DDC-8

8. W.Skulski APS April/2003 Signal from a pocket NIM pulser digitized with the DDC-8 at 40 Msamples/s * 10 bits Excellent response to a very fast pulse seen with the “spy channel” DDC-8: how fast is the response? t pulse < t sampling. Digitization made possible by the Nyquist filter f filter = 1/4 f sampling Latency = 300ns Input pulse

9. W.Skulski APS April/2003 Response to scintillation pulses DDC-8 firmware is under development. Results obtained with DDC-1, 48 MHz @ 12 bits. Very fast plastic BC-404: t pulse < t sampling. NaI(Tl): t pulse > t sampling. CsI(Tl): particle identification. Phoswich: two-component FAST-SLOW pulses.

10. W.Skulski APS April/2003 Signal from a Bicron BC-404 detector digitized with the 1-channel prototype at 48 Msamples/s * 12 bits Excellent response to a very fast pulse 1 sample = 20.8 ns1 sample = 0.2 ns Tek screen for reference Fast plastic scintillator, t pulse < t sampling.

11. W.Skulski APS April/2003 Signals from a Bicron 2”x2” NaI(Tl) detector digitized with the 1-channel prototype at 48 Msamples/s * 12 bits 137 Cs Medium-fast scintillator pulses: NaI(Tl)

12. W.Skulski APS April/2003  -ray 1 cm 3 CsI(Tl) + phototube 1-channel prototype at 48 Msamples/s * 12 bits  -particle Slow scintillator pulses: CsI(Tl)

13. W.Skulski APS April/2003  raditional slow-tail representation 1 cm 3 CsI(Tl) + phototube 1-channel prototype at 48 Msamples/s * 12 bits nat Th radioactive source “tail” window not yet optimized PID = TAIL / TOTAL Note energy-independent PID Particle ID from CsI(Tl) PRELIMINARY

14. W.Skulski APS April/2003 CsI(Tl) crystal cosmic ray phototube teflon Bicron BC-404 FAST SLOW Signal from a phoswich detector digitized with the DDC-1 48 Msamples/s at 12 bits FAST clearly separated from SLOW 1 sample = 20.8 ns

15. W.Skulski APS April/2003 Applications of the DDC-8 The combo system DDC-8 and XLM-72. Online energy and particle ID. DwarfBall and SuperBall. Real-time trigger logic. Phobos @ RHIC. Standalone table-top 8-channel digitizer. DPP algorithm development. Standalone data acquisition and histogramming. Convenient USB interface.

16. W.Skulski APS April/2003 Nominal Collision Region Analog signals: Paddles, Cerenkov, ZDC. Logic signals from conventional NIM. 1st level processing: DDC-8. 2nd level processing: XLM-72. Accept/reject event within about 1  sec. Note: digitization latency = 300ns. Application: online PHOBOS trigger Trigger counters, one side. (ZDCs are off picture.) PHOBOS @ RHIC

17. W.Skulski APS April/2003 Neutron Calorimeter SuperBall. 16 m 3 organic liquid scintillator. Online pulse shape analysis with DDC. Charged particle ID with CsI(Tl)/plastic. Neutron capture counting and timing. 1st level processing: DDC-8. 2nd level processing: XLM-72. Application: SuperBall + DwarfBall 4  charged particle detector DwarfBall/DwarfWall. Plastic+CsI(Tl) phoswich detectors.

18. W.Skulski APS April/2003 8 chan XLM-72 900 MFLOPs 4 MB 40,000 gates DAQ 8 chan 32 flash ADCs 32*NIM out 8 chan 64*NIM in On-board monitoring 1.2 million gates in the FPGAs On-the-fly data preprocessing Four independent parallel interfaces, 100+ MB/s. VME Flash ADC front end

19. W.Skulski APS April/2003 Digital interface DSP 900 MFLOPs FPGA 2Mb SRAM 72 ECL lines (four independent 17-bit connectors + 4 extra bits). TTL-ECL

20. W.Skulski APS April/2003 Plans April ‘03: workshop: DPP in PHOBOS @RHIC. Work out the details and proposed solutions for PHOBOS. Winter ‘03: enhance the system DDC+XLM. 40+ channels per VME slot. More channels, 12 bits, etc. High-resolution spectroscopy. Mundane details. DPP algorithm development for FPGA and embedded micro. Firmware and embedded software. User interfaces.