# IFT 201: Unit 1 Lecture 1.3: Processor Architecture-3

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IFT 201: Unit 1 Lecture 1.3: Processor Architecture-3
Dr. Joseph M Kuitche Information Technology ASU Polytechnic School

Review of previous lecture
Memory operands: load and store Immediate operands (addi) are used to avoid load instruction on constants Most architecture reserve a special register (usually \$zero) for the constant 0 Any integer quantity can be represented exactly using any base or radix It is important to get proficient with base-2 or binary system You can convert from decimal to binary using either subtraction or division methods When assuming only positive numbers, we are said to be using unsigned representation In signed representation, the MSB indicates the sign of the number: 1 for negative number, and 0 for positive numbers Signed binary integers may be expressed in 3 different ways, of which 2’s complement representation is mostly used To represent a number using more bits, just replicate the sign bit to the left

Representing Instructions
The University of Adelaide, School of Computer Science 24 April 2017 Representing Instructions Instructions are encoded in binary Called machine code MIPS instructions Encoded as 32-bit instruction words Small number of formats encoding operation code (opcode), register numbers, … Regularity! Register numbers \$t0 – \$t7 are reg’s 8 – 15 \$t8 – \$t9 are reg’s 24 – 25 \$s0 – \$s7 are reg’s 16 – 23 §2.5 Representing Instructions in the Computer Chapter 2 — Instructions: Language of the Computer — 3 Chapter 2 — Instructions: Language of the Computer

MIPS Register Set

FIGURE 2.1 MIPS assembly language revealed in this chapter. This information is also found in Column 1 of the MIPS Reference Data Card at the front of this book. Copyright © 2014 Elsevier Inc. All rights reserved.

MIPS INSTRUCTIONS FORMATS Unconditional jump (jump) instruction
Arithmetic, Logic instructions R-format op rs rt rd shamt funct 6 bits 5 bits Data transfer, addi, Branch instructions I-format op rs rt address 6 bits 5 bits 16 bits Unconditional jump (jump) instruction J-format op address 6 bits 26 bits op rs rt rd shamt funct Operation code (opcode) 1st source register # 2nd source register # Destination register # Shift amount 00000 for now Function code

MIPS INSTRUCTIONS - Arithmetic Arithmetic, logic instruction format
Category Instruction Example Meaning Comments Arithmetic add add \$at, \$at, \$v1 \$at = \$v0 + \$v1 3 operands, data in registers subtract sub \$at, \$v0, \$v1 \$at = \$v0 - \$v1 R-format op rs rt rd shamt funct Arithmetic, logic instruction format Field size 6 bits 5 bits Name Format Example Comments add R 2 3 1 32 add \$at, \$v0, \$v1 sub 34 sub \$at, \$v0, \$v1

R-format Example (Arithm)
The University of Adelaide, School of Computer Science 24 April 2017 R-format Example (Arithm) op rs rt rd shamt funct 6 bits 5 bits add \$t0, \$s1, \$s2 special \$s1 \$s2 \$t0 add 17 18 8 32 000000 10001 10010 01000 00000 100000 = Chapter 2 — Instructions: Language of the Computer — 8 Chapter 2 — Instructions: Language of the Computer

Activity – Arithmetic Provide the MIPS assembly code, binary, and hexadecimal representations of the high-level instruction below. f = g + h – 5; Assume the variables f, g, and h are stored in registers \$s0, \$s1, and \$s2 respectively

The University of Adelaide, School of Computer Science
24 April 2017 Logical Operations Instructions for bitwise manipulation §2.6 Logical Operations Operation C Java MIPS Shift left << sll Shift right >> >>> srl Bitwise AND & and, andi Bitwise OR | or, ori Bitwise NOT ~ nor Useful for extracting and inserting groups of bits in a word Chapter 2 — Instructions: Language of the Computer — 10 Chapter 2 — Instructions: Language of the Computer

The University of Adelaide, School of Computer Science
24 April 2017 Shift Operations op rs rt rd shamt funct 6 bits 5 bits shamt: how many positions to shift Shift left logical Shift left and fill with 0 bits sll by i bits multiplies by 2i Shift right logical Shift right and fill with 0 bits srl by i bits divides by 2i (unsigned only) Chapter 2 — Instructions: Language of the Computer

The University of Adelaide, School of Computer Science
24 April 2017 AND Operations Useful to mask bits in a word Select some bits, clear others to 0 and \$t0, \$t1, \$t2 \$t2 \$t1 \$t0 Chapter 2 — Instructions: Language of the Computer — 12 Chapter 2 — Instructions: Language of the Computer

The University of Adelaide, School of Computer Science
24 April 2017 OR Operations Useful to include bits in a word Set some bits to 1, leave others unchanged or \$t0, \$t1, \$t2 \$t2 \$t1 \$t0 Chapter 2 — Instructions: Language of the Computer — 13 Chapter 2 — Instructions: Language of the Computer

The University of Adelaide, School of Computer Science
24 April 2017 NOT Operations Useful to invert bits in a word Change 0 to 1, and 1 to 0 MIPS has NOR 3-operand instruction a NOR b == NOT ( a OR b ) nor \$t0, \$t1, \$zero Register 0: always read as zero \$t1 \$t0 Chapter 2 — Instructions: Language of the Computer — 14 Chapter 2 — Instructions: Language of the Computer

Activity – Logic Consider the execution of the program segment below (which consists of all instructions shown) for the MIPS architecture discussed in class. Initial values in registers pertinent to this problem are: \$a0 = 4 and \$t0 = 4032; the values in memory location 1232 is 4000; values are in decimal. Assuming the program segment is stored in memory starting at address (6,000)10 Give the machine-language equivalent for the instruction labeled “End”. INIT: lw \$t1, 1232(\$zero) Top: beq \$zero, \$zero, Nex Sec: addi \$s0, \$t1, -8 \$zero, \$zero, End Nex: \$s0, 0(\$t1) add \$t1, \$t1, \$a0 Key: \$t1, \$t0, Sec \$zero, \$zero, Top End: nand \$s0, \$t1, \$a0

MIPS INSTRUCTIONS – Data transfer & addi Data transfer, branch format
Category Instruction Example Meaning Comments Data transfer load word lw \$at, 100(\$v0) \$at = Memory[\$v ] Data from memory to register store word sw \$a0, 100(\$a2) Memory[\$a2+100] = \$a0 Data from register to memory I-format op rs rt address Data transfer, branch format Field size 6 bits 5 bits 16 bits Name Format Example Comments lw I 35 2 1 100 lw \$at, 100(\$v0) sw 43 6 4 sw \$a0, 100(\$a2)

The University of Adelaide, School of Computer Science
24 April 2017 lw/sw Example op rs rt constant or address offset 6 bits 5 bits 16 bits lw \$t0, 1200(\$t1) lw \$t1 \$t0 offset 35 9 8 1200 100011 01001 01000 = 8D2804B016 Chapter 2 — Instructions: Language of the Computer

The University of Adelaide, School of Computer Science
24 April 2017 addi Example op rs rt constant or address offset 6 bits 5 bits 16 bits addi \$s1, \$s2, 100 addi \$s2 \$s1 constant 8 18 17 100 001000 Chapter 2 — Instructions: Language of the Computer

Activity – lw and addi Consider the execution of the program segment below (which consists of all instructions shown) for the MIPS architecture discussed in class. Initial values in registers pertinent to this problem are: \$a0 = 4 and \$t0 = 4032; the values in memory location 1232 is 4000; values are in decimal. Assuming the program segment is stored in memory starting at address (6,000)10 Give the machine-language equivalent for the instructions labeled “INIT” and “Sec”. INIT: lw \$t1, 1232(\$zero) Top: beq \$zero, \$zero, Nex Sec: addi \$s0, \$t1, -8 \$zero, \$zero, End Nex: \$s0, 0(\$t1) add \$t1, \$t1, \$a0 Key: \$t1, \$t0, Sec \$zero, \$zero, Top End: and \$s0, \$t1, \$a0

Conditional Operations
The University of Adelaide, School of Computer Science 24 April 2017 Conditional Operations Branch to a labeled instruction if a condition is true Otherwise, continue sequentially beq rs, rt, L1 if (rs == rt) branch to instruction labeled L1; bne rs, rt, L1 if (rs != rt) branch to instruction labeled L1; j L1 unconditional jump to instruction labeled L1 §2.7 Instructions for Making Decisions Chapter 2 — Instructions: Language of the Computer — 20 Chapter 2 — Instructions: Language of the Computer

Compiling If Statements
The University of Adelaide, School of Computer Science 24 April 2017 Compiling If Statements C code: if (i==j) f = g+h; else f = g-h; f, g, … in \$s0, \$s1, … Compiled MIPS code: bne \$s3, \$s4, Else add \$s0, \$s1, \$s j Exit Else: sub \$s0, \$s1, \$s2 Exit: … Assembler calculates addresses Chapter 2 — Instructions: Language of the Computer — 21 Chapter 2 — Instructions: Language of the Computer

Activity – Decision For the following C statements, provide the MIPS Assembler using a minimal number of MIPS assembly instructions if (j==k) a = a + 1; a = b + c;

More Conditional Operations
The University of Adelaide, School of Computer Science 24 April 2017 More Conditional Operations Set result to 1 if a condition is true Otherwise, set to 0 slt rd, rs, rt if (rs < rt) rd = 1; else rd = 0; slti rt, rs, constant if (rs < constant) rt = 1; else rt = 0; Use in combination with beq, bne slt \$t0, \$s1, \$s2 # if (\$s1 < \$s2) bne \$t0, \$zero, L # branch to L Chapter 2 — Instructions: Language of the Computer — 23 Chapter 2 — Instructions: Language of the Computer

MIPS INSTRUCTIONS – Conditional branch
Category Instruction Example Meaning Comments Conditional branch branch on equal beq \$8, \$5, L if (\$8==\$5) go to L Equal test and branch. Addr is relative to (PC+4) set on less than slt \$9, \$6, \$23 if (\$6 < \$9) \$9=1 else \$9 = 0 Compare less than; used with beq Field size 6 bits 5 bits 16 bits Comments I-format op rs rt address Data transfer, branch format R-format rd shamt funct Arithmetic, logic instruction format Name Format Example Comments beq I 4 8 5 x beq \$8, \$5, addr x=[addr-(PC+4)]/4 slt R 6 23 9 42 set \$9, \$6, \$23

MIPS INSTRUCTIONS – Unconditional jump

Activity – Branch Consider the execution of the program segment below (which consists of all instructions shown) for the MIPS architecture discussed in class. Initial values in registers pertinent to this problem are: \$a0 = 4 and \$t0 = 4032; the values in memory location 1232 is 4000; values are in decimal. Assuming the program segment is stored in memory starting at address (6,000)10 Give the machine-language equivalent for the instruction labeled “Key”. INIT: lw \$t1, 1232(\$zero) Top: beq \$zero, \$zero, Nex Sec: addi \$s0, \$t1, -8 \$zero, \$zero, End Nex: \$s0, 0(\$t1) add \$t1, \$t1, \$a0 Key: \$t1, \$t0, Sec \$zero, \$zero, Top End: and \$s0, \$t1, \$a0

Compiling Loops C Assembly while(j != 0) { /* loop body */
t = t + j--; } Assembly beq \$t0,\$zero,done ; loop body add \$s0, \$s0, \$t0 addi \$t0, \$t0, -1 done … Assuming \$t0 = j \$s0 = t

Activity – Loop For the following C statements, provide the MIPS Assembler using a minimal number of MIPS assembly instructions while (a != 5) { t = a; a = b + a--; }

The University of Adelaide, School of Computer Science
24 April 2017 Memory Layout Text: program code Static data: global variables e.g., static variables in C, constant arrays and strings \$gp initialized to address allowing ±offsets into this segment Dynamic data: heap E.g., malloc in C, new in Java Stack: automatic storage Chapter 2 — Instructions: Language of the Computer — 29 Chapter 2 — Instructions: Language of the Computer