1. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Slide 1 Spezielle Anwendungen des VLSI – Entwurfs Applied VLSI design Course and contest Results of Phase 3 Sebastian Kruse

2. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Optimizations Slide 8

3. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Carry Skip Adder Slide 8 CLA 0101 0101 0101

4. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Han Carlson Brent Kung Han Carlson / Brent Kung Slide 4 Source: Binary Adder Architectures for Cell-Based VLSI and their Synthesis, Prof.Dr. W. Fichtner, 1997

5. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Comparison between FPGA and ASIC Slide 8 FPGA { Frequency / Area }  Carry Skip: 324.044 MHz / 143 LUT  Ripple Carry:426,439 MHz / 109 LUT  Han Carlson:332,779 MHz / 128 LUT  Brent Kung:293,083 MHz / 135 LUT ASIC { Frequency / P dyn / P leak }  Carry Skip: 356 MHz / 3,156 nW / 19,330 nW  Ripple Carry:390 MHz / 3,135 nW / 19,185 nW  Han Carlson:356 MHz / 3,146 nW / 19,241 nW  Brent Kung:356 MHz / 3,148 nW / 19,244 nW

6. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Filter response Slide 9 FPGA ASIC

7. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Results Slide 10 Mandatory values for ASIC Frequency f900,00 MHz Area A2864.67 Power P Dyn 3,135 nW Power P Leak 19,185 nW # Pipeline Stages8 Metric (10 -3 / (pJ)²)[2,532] Used parameters for synthesis in Synopsys: set frequency 0.001 compile_ultra set_max_leakage_power 0 mw set_max_dynamic_power 0 mw set_wire_load_mode top

8. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Future improvements Change type of adder (phase 3)  Brent Kung adder  Han Carlson adder  Carry skip adder Only do an addition for important digits Summation compression (Wallace tree)  Carry save representation Slide 11

9. Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock Thank you for your attention! Slide 12