1. Efficient Loop Handling for DSP algorithms on CISC, RISC and DSP processors M. Smith, Electrical and Computer Engineering, University of Calgary, Alberta, Canada smithmr @ ucalgary.ca This presentation will probably involve audience discussion, which will create action items. Use PowerPoint to keep track of these action items during your presentation In Slide Show, click on the right mouse button Select “Meeting Minder” Select the “Action Items” tab Type in action items as they come up Click OK to dismiss this box This will automatically create an Action Item slide at the end of your presentation with your points entered.

2. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 2 / 33 Key elements in DSP algorithms Instruction fetches – must be efficient Data fetches / stores – often multiple – must be efficient Multiplication – must be efficient and accurate and remain precise Addition – must be efficient and accurate and remain precise Decision logic to control all the operations above – must be efficient Program flow is key control operation

3. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 3 / 33 To be tackled today Performing operations on an array Loop overhead can steal many cycles Loop overhead -- depends on implementation Standard loop with test at the start -- while ( ) Initial test with additional test at end -- do-while( ) Down-counting loops Special Efficiencies CISC -- hardware RISC -- intelligent compilers DSP -- hardware

4. 11/23/2015 ENCM515 -- Background to Audio Channel Modelling Copyright smithmr@ucalgary.ca 4 / 33 No relative delay modelled into the audio channel -- then sound perceived in centre of head Modelling a relative delay into the right ear audio channel. Sound arrival will shift sound to left as “sound” seems to get to left ear first DELAY 0 DELAY_LEFT DELAY_RIGHT

5. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 5 / 33 FIFO buffer update via Memory Move Implement a delay line – Try zero delay on left channel and large delay on right delay. Then try to read into a microphone void MemoryMove_Delay_CPP(void) { int count; // Insert new value into the back of the FIFO delay line left_delayline[0 + LEFT_DELAY_VALUE] = channel1_in; // Grab delayed value from the front of the FIFO delay line channel1_out = left_delayline[0]; // Update the FIFO delay line using inefficient // memory-to-memory moves for (count = 0; count < LEFT_DELAY_VALUE; count++) left_delayline[count] = left_delayline[count + 1]; }

6. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 6 / 33 Example – Pointer FIFO Delay Line float FIFO[N]; float *pt_in = &FIFO[DELAY]; float *pt_out = &FIFO[0]; void PointerFIFO_CPP(void) { // Insert new value into the back of the FIFO delay line *pt_in ++ = channel1_in (Read pt_in value, use it, store new pt_in value) // Grab delayed value from the front of the FIFO delay line *channel1_out = *pt_out ++ if (pt_in > &left_delay[0 + LEFT_DELAY_VALUE]) then pt_in = pt_in – (LEFT_DELAY_VALUE); if (pt_out > &left_delay[0 + LEFT_DELAY_VALUE]) then pt_out = pt_out – (LEFT_DELAY_VALUE) } Requires additional reads and stores of “static” memory locations where pointers are stored Requires compares and jumps – pipeline issues on jumps

7. 11/23/2015 ENCM515 -- Background to Audio Channel Modelling Copyright smithmr@ucalgary.ca 7 / 33 Labs. 4 -- delay line -- Concept Get “ambience” by taking into account constructive and destructive interference around the face. This implies knowing characteristics of “audio channel” and modelling using an FIR filter -- 2 FIR filters per speaker -- processing requirement increasing FILTER 330 LEFT FILTER 30 LEFT FILTER 30 RIGHT FILTER 330 RIGHT

8. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 8 / 33 Real-time FIR Filter float fircoeffs_30[], fircoeffs[330]; void FIRFilter(void) { // Insert new value into FIFO delay line left_delayline[0 + N] = (float) channelLeft_in; right_delayline[0 + N] = (float) channelRight_in; channel_one_30 = channel_one 330 = 0; Need equivalent of following loop for EACH sound source for (count = 0, count < FIRlength - 1, count++) { channel_one_30 = channel_one_30 + left_delayline [count] * fir_30(count); channel_one_330 = channel_one_330 + right_delayline [count]* fir_330[count]; } channelLeft_out = (int) channel_one_30 + scale_factor * channel_one_30 ditto 2 Update Left Channel delay line; Update Right Channel Delay line }

9. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 9 / 33 Real-time FIR – Hard-coded loop channel_one_30 = channel_one_30 + arrayleft[0] * fir_30(0); channel_one_30 = channel_one_30 + arrayleft[1] * fir_30(1); channel_one_30 = channel_one_30 + arrayleft[2] * fir_30(2); channel_one_30 = channel_one_30 + arrayleft[3] * fir_30(3); channel_one_30 = channel_one_30 + arrayleft[4] * fir_30(4); channel_one_30 = channel_one_30 + arrayleft[5] * fir_30(5); channel_one_30 = channel_one_30 + arrayleft[6] * fir_30(6); channel_one_30 = channel_one_30 + arrayleft[7] * fir_30(7); No loop overhead heavy memory penalty -- FIR filters – 300 taps * 4 filters Using pt++ type memory operations rather than direct memory access with offset is faster ----- on SOME processors!!

10. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 10 / 33 Timing required to handle DSP loops for k = 0 to (N-1) -- Could require many lines to code Body of Code -- BofC cycles -- Could be 1 line Endfor -- Could require many lines to -- code, jumps and counter updates Important feature -- how much overhead time is used in handling the loop construct itself? Three components Set up Time Body of code time -- BofC cycles Handling the loop itself

11. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 11 / 33 Basic Loop body Set up loop -- loop overhead -- done once Check conditions -- loop overhead -- done many times Do Code Body -- done many times -- useful Loop Back + counter increment -- loop overhead -- many Define Loop Efficiency = Useful cycles / Total cycles = N * Tcodebody -------------------------------------------- Tsetup + N * (Tcodebody + Tconditions + Tloopback) Different Efficiencies depending on the size of the loop Need to learn good approximation techniques and recognize the two extremes

12. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 12 / 33 3 different basic loop constructs While loop Main compare test at top of loop Modified do-while loop with initial test Initial compare test at top Main compare test at the bottom of the loop Down-counting do-while loop with initial test No compare operations in test. Relies on the setting of condition code flags during adjustment of the loop counter. Can increase overhead in some algorithms

13. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 13 / 33 Data from the memory appears near the end of the read cycle Clements -- Microprocessor Systems Design PWS Publishing ISBN 0-534-94822-7

14. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 14 / 33 Review -- CISC processor instruction phases Fetch -- Obtain op-code PC-value out on Address Bus Instruction op-code at Memory[PC] on Data Bus and then into Instruction Register Decode -- Bringing required values (internal or external) to the ALU input. Immediate -- Additional memory access for value -- Memory[PC] Absolute -- Additional memory access for address value and then further access for value -- Memory[Memory[PC]] Indirect -- Additional memory access to obtain value at Memory[AddressReg] Execute -- ALU operation Writeback -- ALU value to internal/external storage May require additional memory accesses to obtain address used during storage May require additional memory operations to perform storage.

15. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 15 / 33 Basic 68K CISC loop -- Test at start MOVE.L #0, count -- Set up -- count in register Fetch instr. (FI4) + Fetch 32-bit constant (FC 2 * 4) + operation (OP0) LOOP: CMP.L #N, count -- (FI4 FC8, OP4 -- 32bit subtract) BGE ENDLOOP Actually ADD.L #(ENDLOOP - 4), PC (ADD OF 16-bit DISPLACEMENT TO PC-- FI4 FC4 OP(0 or 4) ) Body Cycles -- doing FIR perhaps ADD.L #1, count -- (FI4, FC8, OP4) JMP LOOP -- (FI4, FC8, OP4) ENDLOOP: -- This is actually a numerical value (address) N * BodyCycles LOOP EFFECIENCY = --------------------------------------------------------- 12 + N*(28 + BodyCycles + 32) Since (28 + 32) >> 12 (5 times) then ignore startup cycles even if N small

16. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 16 / 33 Check at end -- 68K CISC loop MOVE.L #0, count -- (FI4, FC8, OP0) JMP LOOPTEST -- (FI4, FC8, OP4) NOTE JUMP LOOP: Body Cycles -- doing FIR perhaps ADD.L #1, count -- (FI4, FC8, OP4) LOOPTEST: CMP.L #N, count -- (FI4, FC8, OP4) BLT LOOP -- (FI4, FC4, OP4) N * BodyCycles EFFECIENCY = --------------------------------------------------------- 26 + N*BodyCycles + 44*(N+1) Since 44 > 26 (only 1.8 times) then can’t Ignore startup cycles when N small and Body Cycles small -- Small loop means inefficient

17. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 17 / 33 Down Count -- 68K CISC loop MOVEQ.L #0, array_index -- (FI4, FC0, OP0) MOVE.L #N, count -- (FI4, FC0, OP0) JMP LOOPTEST -- (FI4, FC8, OP4) LOOP: BodyCycles using instructions of form OPERATION (Addreg, Index) ADDQ.L #1, array_index-- (FI4, FC0, OP0?) SUBQ.L #1, count -- (FI4, FC0, OP0?) LOOPTEST : BGT LOOP -- (FI4, FC4, OP4) N * BodyCycles Loop Efficiency = --------------------------------------------------------- 24 + N*BodyCycles + 20*(N+1) (was 44 * (N+1)) Since 20 < 24 then can’t Ignore startup if N small and Body Cycles small

18. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 18 / 33 Down Count -- Possible sometimes MOVEA.L #array_start, Addreg-- (FI4, FC0, OP0) MOVE.L #N, count -- (FI4, FC0, OP0) JMP LOOPTEST -- (FI4, FC8, OP4) LOOP: BodyCycles using autoincrement mode OPCODE (Addreg)+ SUBQ.L #1, count -- (FI4, FC0, OP0?) LOOPTEST : BGT LOOP -- (FI4, FC4, OP4) N * BodyCycles Loop Efficiency = --------------------------------------------------------- 24 + N*BodyCycles + 16*(N+1) (was 20 * (N+1)) Since 16 < 24 then can’t Ignore startup if N small and Body Cycles small NOTE -- Number of cycles needed in body of the loop decreases in this case

19. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 19 / 33 Loop Efficiency on CISC processor Efficiency depends on how loop constructed Standard while-loop Check at end -- modified do-while Down counting -- with/without auto-incrementing addressing modes Compiler versus hardcode efficiency See Embedded System Design magazine Sept./Oct 2000 Local copy available on ENCM515 web-pages What happens with different processor architectures?

20. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 20 / 33 Check at end -- 29K RISC loop CONST count, 0 -- (1 cycle) JUMP LOOPTEST -- (1 cycle) NOP -- (1 cycle -- delay slot) LOOP: Bodycycles -- autoincrementing mode -- NOT AN OPTION ON 29K ADDU count, count, 1 -- (1 cycle) LOOPTEST: CPLE TruthReg, count, N -- (1 cycle should be 2 -- register forwarding) (Boolean Truth Flag in TruthReg -- which could be any register) JMPT TruthReg LOOP -- (1 cycle) NOP -- (1 cycle -- delay slot) N * BodyCycles Loop Efficiency = --------------------------------------------------------- 3 + N * BodyCycles + 4*(N+1) Since 4 = 3 then can’t Ignore startup if N small and Body Cycles small Since dealing with single cycle operations -- body cycle count smaller than CISC. This means that the loop overhead become more problematic if the processor efficient

21. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 21 / 33 Down Count -- 29K RISC loop CONST index, 0 -- 1 cycle JUMP LOOPTEST -- 1 cycle CONST count, N -- in delay slot LOOP: BodyCycles SUBU count, count, 1 -- 1 cycle LOOPTEST: CPGT TruthReg, count, 0 -- 1 cycle JMPT TruthReg, LOOP -- 1 cycle ADDS index, index, 1 -- in delay N * BodyCycles Loop Efficiency = --------------------------------------------------------- 3 + N*BodyCycles + 4*(N+1)

22. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 22 / 33 Efficiency on RISC processors Not much difference between Test at end, Down count loop format HOWEVER body-cycle count has decreased Processor is highly pipelined -- Loop jumps cause the pipeline to stall Need to take advantage of delay slots Efficiency depends on DSP algorithm being implemented? What about DSP processors? Architecture is designed for efficiency in this area.

23. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 23 / 33 Check at end -- ADSP-21K loop count, = 0; -- (1 cycle) number = N; -- (1 cycle) JUMP LOOPTEST (DB); -- (1 cycle) – jump to loop end NOP; -- (1 cycle -- delay slot) NOP; -- (1 cycle -- delay slot) LOOP: BODYCYCLES count = count + 1; -- (1 cycle) LOOPTEST Comp(count, number); -- (1 cycle) IF LT JUMP LOOP (DB); -- (1 cycle) NOP; -- (1 cycle -- delay slot) NOP; -- (1 cycle -- delay slot) N * BodyCycles EFFICIENCY = --------------------------------------------------------- 5 + N*BodyCycles + 5*(N+1)

24. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 24 / 33 Speed improvement -- Possible? count = 1; -- (1 cycle) number = N; -- (1 cycle) JUMP LOOPTEST (DB); -- (1 cycle) count = count - 1; -- (1 cycle -- delay slot) ADJUST number = number - 1; -- (1 cycle -- delay slot) LOOP: BODYCYCLES count = count + 1; -- (1 cycle) LOOPTEST: Comp(count, number); -- (1 cycle) IF LT JUMP LOOP (DB); -- (1 cycle) count = count + 1;-- (1 cycle -- delay slot) NOP; -- (1 cycle -- delay slot) N * BodyCycles EFFICIENCY = --------------------------------------------------------- 5 + N*BodyCycles + 4*(N+1)

25. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 25 / 33 Down Count -- ADSP-21K loop number = 0; -- (1 cycle) JUMP (PC, LOOPTEST) (DB); -- (1 cycle) index = 0; -- (1 cycle -- in delay slot) count = N ; -- (1 cycle -- in delay slot) LOOP: Bodycycles count = count - 1; -- (1 cycle) LOOPTEST Comp(count, number); -- (1 cycle) IF GT JUMP (PC, LOOP) (DB); -- (1 cycle) index = index + 1; -- (1 cycle -- delay slot) NOP; -- (1 cycle -- delay slot) N * BodyCycles Loop Efficiency = --------------------------------------------------------- 4 + N*BodyCycles + 5*(N+1)

26. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 26 / 33 Improved Down Count -- ADSP21K loop Is code valid -- or 1 off in times around loop? number = -1; -- Bias the loop counter (1 cycle) JUMP (PC, LOOPTEST) (DB); -- (1 cycle) index = 0; -- (1 cycle -- in delay slot) count = (N-1); -- (1 cycle -- in delay slot) LOOP: Body cycles LOOPTEST Comp(count, number); -- (1 cycle) IF GT JUMP (PC, LOOP); -- (1 cycle) index = index + 1; -- (1 cycle -- delay slot) count = count - 1; -- (1 cycle -- delay slot) N * BodyCycles Loop Efficiency = --------------------------------------------------------- 4 + N*BodyCycles + 4*(N+1)

27. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 27 / 33 Faster Loops Need to go to special features CISC -- special Test, Conditional Jump and Decrement in 1 instruction RISC -- Change algorithm format DSP -- Special hardware for loops Maximum of six-nested loops (or just 2 on some processors) Can be a hidden trap when mixing “C” and asm code

28. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 28 / 33 Recap -- 68K CISC loop down count MOVEQ.L #0, index -- (FI4, FC0, OP0) MOVE.L #N, count -- (FI4, FC0, OP0) JMP LOOPTEST -- (FI4, FC8, OP4) LOOP: BodyCycles ADDQ.L #1, index -- (FI4, FC0, OP0?) SUBQ.L #1, count -- (FI4, FC0, OP0?) LOOPTEST : BGT LOOP -- (FI4, FC4, OP4) N * BodyCycles Loop Efficiency = --------------------------------------------------------- 24 + N*BodyCycles + 20*(N+1) Since 24=20 then can’t Ignore startup if N small and Body Cycles small

29. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 29 / 33 Hardware 68K CISC loop MOVEQ.L #0, index -- (FI4 FC0 OP0) MOVE.L #(N-1), count -- (FI4 FC0 OP0) JMP LOOPTEST -- (FI4, FC8, OP4) LOOP: BodyCycles ADDQ.L #1, index -- (FI4, FC0 OP0?) LOOPTEST: DBCC count, LOOP -- (FI4, FC4, OP4) N * BodyCycles Loop Efficiency = ------------------------------------------------- 24 + N*BodyCycles + 16*(N+1) Possibility that Efficiency almost 100% if the Body Instructions are small enough to fit into cache

30. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 30 / 33 Custom loop hardware on RISC For long loops -- loop overhead small -- no need to be concerned about the loop overhead (unless loop in loop) For small loops -- unroll the loop so that hardcoded 20 instructions rather than 1 instruction looped 20 times For medium loops -- advantage over CISC normally is that instructions more efficient -- 1 cycles compared to 4 -- 8 cycles For medium loops -- advantage over DSP normally is that instructions more efficient 1 RISC cycle compared to 2 DSP cycles -- (not 21K since 1 to 1) For more information See the Micro 1992 articles See the CCI articles

31. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 31 / 33 21k Processor architecture

32. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 32 / 33 Recap -- Improved Down Count -- 21K DSP loop number_R1 = -1 -- (1 cycle) JUMP (PC, LOOPTEST) (DB) -- (1 cycle) index_M4 = 0 -- (1 cycle -- in delay slot) count_R2 = (N-1) -- (1 cycle -- in delay slot) LOOP: Body cycles LOOPTEST Comp(count,_R2 number_R1)-- (1 cycle ) IF GT JUMP (PC, LOOP) -- (1 cycle) index _M4= index _M4+ 1 -- (1 cycle -- delay slot) count _R2= count _R2- 1 -- (1 cycle -- delay slot) N * BodyCycles Loop Efficiency = --------------------------------------------------------- 4 + N*BodyCycles + 4*(N+1)

33. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 33 / 33 Hardware Loop -- 21K DSP loop count_R0 = N -- (1 cycle) count_R0 = PASS count_R0-- (1 cycle) sets the condition codes with out doing math (allows parallel operation IF LE JUMP (PC, PASTLOOP) (DB) -- (1 cycle) index = 0 -- (1 cycle -- in delay slot) nop -- (1 cycle -- in delay slot) HARDWARE_LOOP: LCNTR = count_R0; do (PC, PASTLOOP-1) until LCE -- 1 cycle -- parallel instruction Body-cycles PASTLOOP:Last cycle of loop is at location PASTLOOP -1 Rest of the program code N * BodyCycles Loop Efficiency = --------------------------------------------------------- = 100% 6 + N*BodyCycles

34. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 34 / 33

35. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 35 / 33 DSP Hardware loop Efficiency from a number of areas Hardware counter No overhead for decrement No overhead for compare Pipelining efficient Processor knows to fetch instructions from start of loop, not past the loop Has some problems if loop size is too small -- loop timing is longer than expected as processor needs to flush the pipeline and restart it

36. 11/23/2015 ENCM515 -- High Speed Loops -- Hardware and Software Copyright smithmr@ucalgary.ca 36 / 33 Tackled today Performing access to memory in a loop Loop overhead can steal many cycles Loop overhead -- depends on implementation Standard loop with test at the start -- while ( ) Initial test with test at end -- do-while( ) Down-counting loops Special Efficiencies CISC -- hardware RISC -- intelligent compilers DSP -- hardware