1. UNIVERSITY OF ROSTOCK Institute of Applied Microelectronics and Computer Science Single-Rail Self-timed Logic Circuits in Synchronous Designs Frank Grassert, Dirk Timmermann Department of Electrical Engineering and Information Technology Richard-Wagner-Str. 31, D-18119 Rostock-Warnemuende, Germany http://www-md.e-technik.uni-rostock.de frank.grassert@etechnik.uni-rostock.de –Only small timing differences between parallel paths allowed –Intensive timing calculations Solution 1 – inverted outputs: Using the dynamic node as inverted output Requirements: Usage of a basic n-block structure Adherence to necessary timing specifications Application to small logic blocks with limited depth or data paths with small runtime differences Condition for precharge of the inputs: c)No path to ground, if all inverted nodes are already precharged but the non- inverted (DOMINO) outputs are not Structure of single-rail DOMINO and timing diagram DOMINO stage a) b)c) Conditions for evaluation: a)One series transistor with non-inverted (DOMINO) input b)Arrival of non-inverted input signals delayed to the inverted input signals Solution 2 – completion detection: Generation of the self-timed signals from independent outputs of different (two or more) gates Requirements: At least one output goes high Small runtime differences Completion detection in dual-rail structures: from a single gate with complementary outputs = Completion detection in single-rail structures: from outputs of different gates II. Solutions Dynamic Logic Single-Rail e.g. DOMINO Dual-Rail Differential logic styles (e.g. DCVSL) „Complementary single-rail“ (e.g. DOMINO) –Only non-inverting logic functions –High, constant power consumption –About double area than single-rail +Lower power consumption +About half area than dual-rail +Smaller output load (fast) +Less clock transistors +Easy generation of self-timed signals +Self-timed structures: Latch-free evaluation (fast) Reduced clock load (power) Reduced clock skew sensitivity Idea: Combination of single-rail logic with self-timed structures! Problem 1: No inverted outputs in single rail Problem 2: Completion detection for self-timed structures I. Problem Eases completion detection Ensures the change of the level of at least one bit DigitSelf-timed representation -110 001 111 free00 – precharged Signed-Digit representation Digit representation: Self-timed Structure: Short chains for small runtime differences: 3-10 stages Generation of the clock signal at the following stage Clocking the last stage by the global clock signal Storage of information between last and second last stages Successive evaluation of all stages Control of precharge and evaluation phase of the stages by the self-timed scheme Modified self-timed scheme for single-rail dynamic logic III. Architecture & Example Signed-Digit (SD) adder: 1-bit SD-adder self-timed cell Three dynamic stages Several gates per stage Self-timed SD-adder Combination of 1-bit adder cells Six successive dynamic stages trough consecutive blocks IV. Result: Single-Rail Self-timed Signed-Digit Adder +Low power consumption +Small area +Fast, latch-free evaluation +Reduced clock load +Single phase clock Comparison of the SD-adder in single-rail self-timed DOMINO logic and complementary DOMINO Power (  W/MHz): 30 21 DOMINOSingle-rail self-timed DOMINO Max. delay (ns) 4,5 4 Area (transistor no.) 1806 1055 Area for the self-timed logic Features: