1. TRAMS PROJECT TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS FP7 248789 Y1 EC Review Meeting April 12 th 2011 FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011

2. FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 AGENDA 1. Introduction10.30 2. Project management & organization (WP6)11.30 Lunch12.00 3. Detailed review of technical Work Packages (WP1-WP4) 13.30 4. Dissemination and exploitation of results (WP5) 15.50 5. Q&A16.20 6. Breakdown16.45 7. Conclusions17.30 Closing18.00

3. Power point presentations FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 IN public/me.com/rubio2010 Intranet of the project “Reviewers area”

4. FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 AGENDA 1. Introduction10.30 2. Project management & organization (WP6)11.30 Lunch12.00 3. Detailed review of technical Work Packages (WP1-WP4) 13.30 4. Dissemination and exploitation of results (WP5) 15.50 5. Q&A16.20 6. Breakdown16.45 7. Conclusions17.30 Closing18.00

5. FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 1. Introduction (45’+15’) 1.1 Welcome and agenda presentation 1.2 General Project Objectives and Milestones 1.3 Modifications during Y1 respect original DoW 1.4 Milestones and deliverables 1 st year 1.5 Use of resources Y1 1.6 Work plan summary for the 2 nd year 1.7 Modifications respect original DoW for 2 nd and 3 rd years

6. FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 1. Introduction 1.1 Welcome and agenda presentation 1.2 General Project Objectives and Milestones 1.3 Modifications during Y1 respect original DoW 1.4 Milestones and deliverables 1 st year 1.5 Use of resources Y1 1.6 Work plan summary for the 2 nd year 1.7 Modifications respect original DoW for 2 nd and 3 rd years

7. FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 1. Introduction 1.1 Welcome and agenda presentation 1.2 General Project Objectives and Milestones 1.3 Modifications during Y1 respect original DoW 1.4 Milestones and deliverables 1 st year 1.5 Use of resources Y1 1.6 Work plan summary for the 2 nd year 1.7 Modifications respect original DoW for 2 nd and 3 rd years

8. Motivation: Research on Memory technologies for terascale multicore microprocessors FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 MOTIVATION Memories are a key technology driver in semiconductor industry, having an extremely important role in terascale multicore microprocessors In such systems cores and memory may exhibit high failure rates due to process variations and devices degradation mechanisms.

9. FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Pictures from Intel Corporation MOTIVATION

10. Motivation FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011

11. 1.2 General project and objectives FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Objectives of the TRAMS project To investigate the impact of statistical variability and reliability of near and beyond the end of the ITRS devices on Terabit memory design. (Sub-16nm bulk (18,13nm) CMOS,Sub 10nm Finfet, 15nm III-V/Ge and CNT) (WP1-WP2) To design,implement, deploy and assess compensating techniques and countermeasures at circuit and microarchitectural level for memories used in multicore processors (WP3-WP4) To develop a methodology for specifying and implementing performance-, power- and reliability –aware reconfiguration policies for multicore processor. (WP4)

12. 1.2 General project and objectives FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 THE CONSORTIUM

13. 1.2 General project and objectives FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011

14. 1.2 General project and objectives FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 4 TECHNICAL WPs, 15 TASKS

15. 1.2 General project and objectives FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 WORK PACKAGE 1 (WP1) TitlePDK for end of roadmap transistors in the presence of statistical variability and reliability 81 PMs LeaderUOG (71)Other participants: UPC (6), Imec (4) Objectives To design the bulk, FinFET, III/V and CNT devices To extract nominal compact models for them To consider the initial variability and the aging To extract statistical compact models of fresh and degraded devices TasksT1.1. Design of the devices. Nominal compact models. T1.2 Extraction of statistical compact models for fresh devices. T1.3 Extraction of statistical reliability compact models for degraded devices T1.4 Extraction of reliability injectors Deliverables:D1.1 (bulk), D1.2 (CNT), D1.3 (FinFET), D1.4 (III-V/Ge)

16. 1.2 General project and objectives FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 WORK PACKAGE 2 (WP2) TitleModelling and analysis of faulty components at circuit level. 45 PMs LeaderImec (30.5)Other participants: UPC (11.5), UOG (3) Objectives To develop a method for a prototype tool flow for Variability and Reliability –aware modelling of SRAM blocks for the different technologies. TasksT2.1 Variability and Reliability modelling toolflow for bulk. T2.2 Variability modelling toolflow for FinFET SRAM blocks. T2.3 Towards III-V/Ge, CNT and other Emerging Research Devices Deliverables:D2.1 (bulk), D2.2 (FinFETs), D2.3 (III/V and CNT)

17. 1.2 General project and objectives FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 WORK PACKAGE 3 (WP3) TitleHardware countermeasures at the circuit level105 PMs LeaderUPC (86)Other participants: Imec (13), Intel (6) Objectives Research on the effect of environmental and process variability on the performances of the memory systems Mitigating mechanisms and strategies. Compensating and redundant structures Method and prototype tool flow for run-time monitoring. TasksT3.1 Mitigation of the impact of variability. Redundant circuits. T3.2 Countermeasure techniques based on environmental variables, on compensation and reconfiguration mechanisms T3.3 Prototype toolflow for run-time switchable buffer insertion and Reconfiguration. Deliverables:D3.1, D3.2, D3.3, D3.4, D3.5, D3.6

18. 1.2 General project and objectives FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 WORK PACKAGE 4 (WP4) TitleHybrid countermeasures at the micro-architectural and system level 130 PMs LeaderIntel (65)Other participants: UPC (53), Imec (12) Objectives To develop mixed run-time methodologies to predict memory faulty behaviour. To develop run-time methodologies to identify program memory requirements in terms of correctness, performance and power. To develop run-time decision mechanisms for best memory configuration. TasksT4.1 Dynamic characterization of memory and applications. T4.2 Memory reconfiguration. T4.3 Hybrid system scenario countermeasures. T4.4 Global Micro-controller Deliverables:D4.1, D4.2, D4.3, D4.4

19. 1.2 Summary of staff effort FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 21 % 11 % 27 % 33 % 5%5% 5%5% 3%3% 3%3% 43% 16% 20%

20. 1.2 Milestones (as in the DoW) FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 M0M12M24M36 MS0 web MS1 v&r for bulk CMOS MS3 v&r FinFET MS4 reconfiguration MS5 v&r III/V MS6 v&r CNT MS7 Countermeasures circuit level MS8 Countermeasures Micro-arch. level MS9 Final dissemination report

21. Conceptual flow of the project (from DoW work planning) FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 WP1 WP2 WP3 WP4 WP5 Y1Y1 Y2 Y3 PDK x V&R sub 16nm bulk MOSFET idem x FinFET idem x CNT idem x III-V/Ge V&R modelling x bulk CMOS SRAM V&R modelling x FinFET SRAM Towards V&R evaluation x III-V/Ge, CNT and ERD Effect of PTV on different memory cells performance Countermeasure techniques against V&R: Mitigation, Redundancy, Compensation, Reconfiguration, Monitor insertion Dynamic characterization Memory reconfiguration, countermeasures Global MIcrocontroller WEB Dissemination Milestone 2 Milestone 3Milestone 6Milestone 5 Milestone 4 Milestone 7 Milestone 8 Milestone 1 Milestone 9 Device Modelling and analysis methods Cell and circuit level Microarchitecture and system level

22. FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 1. Introduction 1.1 Welcome and agenda presentation 1.2 General Project Objectives and Milestones 1.3 Modifications during Y1 respect original DoW 1.4 Milestones and deliverables 1 st year 1.5 Use of resources Y1 1.6 Work plan summary for the 2 nd year 1.7 Modifications respect original DoW for 2 nd and 3 rd years

23. 1.3 Modifications during Y1 respect original DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 3 modifications no change of objectives no change of milestones Modification of title in deliverable D2.1 Modification work period in T2.2 Exchange of two deliverables in WP3

24. 1.3 Modifications during Y1 respect original DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification 1 (Title of D2.1) D2.1: Report on method for a tool flow for Variability and Reliability modeling for bulk CMOS SRAM blocks. (IMEC) T0+12M Justification Task description refers to a method yet the title method for tool flow may be understood as the expected outcome is a tool while this is not the case. Change ensures correct interpretation

25. 1.3 Modifications during Y1 respect original DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification 2 (T2.2 period) Justification FinFET research in WP1 is concentrated on Y2. Task 2.2: Variability modelling toolflow for FinFET SRAM blocks. [Task Leader: IMEC (10 pms), Duration: [M313-M1824]

26. Conceptual flux of the project (from DoW work planning) FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 WP1 WP2 WP3 WP4 WP5 Y1Y1 Y2 Y3 PDK x V&R sub 16nm bulk MOSFET = x FinFET = x CNT = x III-V/Ge V&R modelling x bulk CMOS SRAM V&R modeling x FinFET SRAM Towards V&R evaluation x III-V/Ge, CNT and ERD Effect of PTV on different memory cells performance Countermeasure techniques against V&R: Mitigation, Redundancy, Compensation, Reconfiguration, Monitor insertion Dynamic characterization Memory reconfiguration, countermeasures Global MIcrocontroller WEB Dissemination Milestone 2 Milestone 3Milestone 5Milestone 6 Milestone 4 Milestone 7 Milestone 8 Milestone 1 Milestone 9 Device Modeling and analysis methods Cell and circuit level Microarchitecture and system level

27. 1.3 Modifications during Y1 respect original DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification 3 (WP3 deliverable order) Justification D3.6 corresponds to the analysis of environmental and process variations. It is necessary to have this analysis before to consider mitigation and countermeasures research. This decision fits with the description of milestone 2 (M12) (v&r analysis for bulk CMOS), and D3.6 pertains to T3.1 that finished M24! D3.6 initially scheduled for M36  M12 D3.1 initially scheduled for M12  M24

28. Conceptual flux of the project (from DoW work planning) FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 WP1 WP2 WP3 WP4 WP5 Y1Y1 Y2 Y3 PDK x V&R sub 16nm bulk MOSFET = x FinFET = x CNT = x III-V/Ge V&R modelling x bulk CMOS SRAM V&R modeling x FinFET SRAM Towards V&R evaluation x III-V/Ge, CNT and ERD Effect of PTV on different memory cells performance Countermeasure techniques against V&R: Mitigation, Redundancy, Compensation, Reconfiguration, Monitor insertion Dynamic characterization Memory reconfiguration, countermeasures Global MIcrocontroller WEB Dissemination Milestone 2 Milestone 3Milestone 5Milestone 6 Milestone 4 Milestone 7 Milestone 8 Milestone 1 Milestone 9 Device Modeling and analysis methods Cell and circuit level Microarchitecture and system level

29. Conceptual flux of the project FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 WP1 WP2 WP3 WP4 WP5 Y1Y1 Y2 Y3 PDK x V&R sub 16nm bulk MOSFET = x FinFET = x CNT = x III-V/Ge V&R modelling x bulk CMOS SRAM V&R modeling x FinFET SRAM Towards V&R evaluation x III-V/Ge, CNT and ERD Effect of PTV on different memory cells performance Countermeasure techniques against V&R: Mitigation, Redundancy, Compensation, Reconfiguration, Monitor insertion Dynamic characterization Memory reconfiguration, countermeasures Global MIcrocontroller WEB Dissemination Milestone 2 Milestone 1 Device Modeling and analysis methods Cell and circuit level Microarchitecture and system level D3.1 D3.6 D3.1

30. FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 1. Introduction 1.1 Welcome and agenda presentation 1.2 General Project Objectives and Milestones 1.3 Modifications during Y1 respect original DoW 1.4 Milestones and deliverables 1 st year 1.5 Use of resources Y1 1.6 Work plan summary for the 2 nd year 1.7 Modifications respect original DoW for 2 nd and 3 rd years

31. 1.4 Milestones (as the DoW) FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 M0M12M24M36 MS0 web MS1 v&r for bulk CMOS MS3 v&r FinFET MS4 reconfiguration MS5 v&r III/V MS6 v&r CNT MS7 Countermeasures circuit level MS8 Countermeasures Micro-arch. level MS9 Final dissemination report ✔ ✔

32. 1.4 Milestones FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 M0M12 MS0 web MS1 v&r analysis for bulk CMOS ✔ ✔ D5.1 (M6) D1.1 (M12) D2.1 (M12) D3.6 (M12)* D4.1 (M12) D5.2 (M12) D6.1 (M12)

33. 1.4 Deliverables for Y1 period FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 MSWPDescription MS0WP5D5.1 TRAMS project website description MS1WP1D1.1 PDK for sub 16nm technology bulk MOSFETs including statistical variability and reliability MS1WP2D2.1 Report on method for variability and reliability modelling for bulk CMOS SRAM blocks MS1WP3D3.6 Report on the effect of environmental and process variations on the variability of memory cells and systems MS1WP4D4.1 Report on the different phase identifier mechanisms MS1WP5D5.2 Dissemination, use plan and joint collaborative actions MS1WP6D6.1 Progress report and cost statement Y1

34. FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 1. Introduction 1.1 Welcome and agenda presentation 1.2 General Project Objectives and Milestones 1.3 Modifications during Y1 respect original DoW 1.4 Milestones and deliverables 1 st year 1.5 Use of resources Y1 1.6 Work plan summary for the 2 nd year 1.7 Modifications respect original DoW for 2 nd and 3 rd years

35. 1.5 Use of resources Y1 FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 16.5 % 26.6 % 40 % 40 % 16.2 % 22.7 % 34.6 % 24.7 % 34.3% 22.9% 18.9% 11.5%

36. FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 1. Introduction 1.1 Welcome and agenda presentation 1.2 General Project Objectives and Milestones 1.3 Modifications during Y1 respect original DoW 1.4 Milestones and deliverables 1 st year 1.5 Use of resources Y1 1.6 Work plan summary for the 2 nd year 1.7 Modifications respect original DoW for 2 nd and 3 rd years

37. 1.4 Milestones FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 M0M12M24M36 MS0 web MS1 v&r for bulk CMOS MS3 v&r FinFET MS4 reconfiguration MS5 v&r III/V MS6 v&r CNT MS7 Countermeasures circuit level MS8 Countermeasures Micro-arch. level MS9 Final dissemination report ✔ ✔ ★ ★ ★ ★ ★

38. 1.5 Work plan summary for the second year FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Y2 plan of work All task actives WPDescription WP1PDK x CNT tech. (D1.2), PDK x FinFETs (D1.3) WP2Method for V & R modelling in FinFET SRAM blocks (D2.2) WP3Mitigation mechanisms (D3.1) Improving reliability through redundancy D(3.2) Mechanisms to detect latency of SRAM D(3.3) Compensation/Reconfiguration mechanisms D(3.4) WP4Identifier mechanisms (D4.1_2) Reconfiguration mechanisms (D4.2) WP5Dissemination, use plan and joint collaborative actions (D5.3) WP6Progress report and cost statement of year 2 (D6.2) WP

39. FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 1. Introduction 1.1 Welcome and agenda presentation 1.2 General Project Objectives and Milestones 1.3 Modifications during Y1 respect original DoW 1.4 Milestones and deliverables 1 st year 1.5 Use of resources Y1 1.6 Work plan summary for the 2 nd year 1.7 Modifications respect original DoW for 2 nd and 3 rd years

40. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Proposed amendments (including modifications Y1) No change of objectives No modification of milestones and schedule of the project No modification of work plan Inclusion of a new deliverable with demonstration in WP4

41. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Amendments in WP1 (2)

42. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification WP1 1 (D1.3 due date) Justification This is required as the results of D1.3 (PDK for sub 16 nm technology FinFET transistors including statistical variability and statistical reliability) are a necessary input to Task T2.2. Move due date D1.3 (FinFET) from M27 to M18

43. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification WP1 2 (D1.2 due date) Justification Balanced distribution of work in WP1, and D1.2 will include the analysis of v&r for 6T and 3T1D cells. Move due date D1.2 (CNT) from M18 to M24

44. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Amendments in WP2 (4)

45. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification WP2 1 (title of D2.1 and D2.2 ) Justification Task description refers to a method yet the title method for tool flow may be understood as the expected outcome is a tool while this is not the case. Change ensures correct interpretation D2.1: Report on method for a tool flow for Variability and Reliability modeling for bulk CMOS SRAM blocks. D2.2: Report on method for a prototype tool flow for Variability modeling forFinFET SRAM blocks. amendment from Y1

46. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification WP2 2 (Move T2.2 and D2.2) Justification D2.2 ends on M18 and should end on M24 because T2.2 ends on M24 it consumes output from D1.3 that ends on M18 Task 2.2: Variability modelling toolflow for FinFET SRAM blocks. [Task Leader: IMEC (10 pms), Duration: [M313-M1824] D2.2: Report on method for Variability modeling forFinFET SRAM blocks. T0+ 1824M amendment from Y1

47. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification WP2 3 (Moving 4PMs from T2.3 to T4.4) Justification Imec moves 4PM from T2.3 to T4.4 to reinforce a demo (new deliverable D4.5) Imec will focus on assessment of III-V technologies and benchmarking against Si under nominal process conditions UPC keeps with CNT and ERD Task 2.3: Towards III-V/Ge, Carbon NanoTubes (CNT) and other Emerging Research Devices. [Task Leader: UPC (11.5 pms), Contribution: IMEC (8.54.5pm) Duration: M18-M36]

48. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Detailed explanation Motivation for move of 4PM from T2.3 to T4.4, clarification of impact on the respective tasks: "Imec needs to reinforce its effort in T4.4 for a demo. To accommodate for the effort increase in T4.4, imec proposes to move 4PM from T2.3 to T4.4. At the same time, the scope of imec work in T2.3, which was not concreted in the original DoW because the activity was considered to be of high risk (see DoW), it can be however now fully defined. At present, imec has already concreted its technical contribution within T2.3 in such way that the proposed technical work addresses the overall objectives of WP2 while these can be achieved within the remaining imec effort in the task (4.5PM). This way, the overall imec effort in the project remains unchanged, hence there is no impact on the requested funding while the overall project objectives remain guaranteed."

49. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification WP2 4 (Moving 3PMs from T2.1 to T2.2) Justification UoG has previously done statistical SRAM analysis based on full statistical bulk MOSFET simulations and feel it would provide more value and novelty to this project to investigate the use of FinFETs, using the SRAM netlist generated by IMEC in T2.2. UoG would like to move the 3PM allocated to T2.1 (Variability and Reliability modelling toolflow for bulk CMOS SRAM blocks) to T2.2 (Variability modelling toolflow for FinFET SRAM blocks).

50. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Amendments in WP3 (3)

51. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification WP3 1 (WP3 deliverable order) Y1 Description modification WP3 1 (WP3 deliverable order) Y1 Justification D3.6 corresponds to the analysis of environmental and process variations. It is necessary to have this analysis before to consider mitigation and countermeasures research. This decision fits with the description of milestone 2 (M12) (v&r analysis for bulk CMOS) D3.6 initially scheduled for M36  M12 D3.1 initially scheduled for M12  M24 amendment from Y1

52. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification WP3 2 (Transfer 18PMs from T3.3 to T3.2) Justification T3.3 as described in DoW describes two different areas: research on a timing monitor insertion technique (Imec 13PMs) research on reconfiguration mechanisms (circuit level) (UPC 18 PMs) Reconfiguration is a mechanism to compensate aging so it is more reasonable in T3.2, so it is a countermeasure No modification of deliverables content, title, schedule Movement of 18PMs from UPC in T3.3 to T3.2

53. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification WP3 3 (Change timing in T3.3 and advance due date D3.5) Task 3.3: Prototype Toolflow for run-time switchable buffer insertion and reconfiguration in SRAMs Design Flow for timing monitor insertion for runtime monitoring of an ASIC during synthesis. [Task Leader: IMEC (13 pms), Contribution: UPC (18 pms). Duration: M1213-M3624]. With changes in the description to make explicit the focus on monitor insertion D3.5: Report on the method toolflow that instantiates the SKM monitor insertion in SRAMs ASICs descriptions. (IMEC) T0+(M36)24 Timing: for deliverable and task are advanced UPC moves work on reconfiguration to T3.2 Imec remains with 13PM Imec will focus on monitors (complementary), already communicated in Brussels meeting with EC Similar to WP2 with an effort of approx 1PY/Y/deliverable imec prefers to focus task T3.3 and its associated deliverable D3.5 in Y2 Justification

54. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Justification UPC moves work on reconfiguration to T3.2 Imec remains with 13PM Imec will focus on monitors (complementary), already communicated in Brussels meeting with EC Similar to WP2 with an effort of approx 1PY/Y/deliverable imec prefers to focus task T3.3 and its associated deliverable D3.5 in Y2

55. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Amendments in WP4 (1)

56. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification WP4 1 (New deliverable) Justification Reinforce evaluation, impact and dissemination of results will be much better Request: add a new deliverable (D4.5) We will prepare a demo showing the most promising results from WP4 in real hardware based on Intel SCC Change: IMEC requests extra 4PMs to be allocated to T4.4 for that purpose

57. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Amendments in WP6 (1)

58. Proposed amendments for DoW FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 Description modification WP6 1 (PTC introduction) Justification The concept was introduced at the creation of the Consortium Agreement. The PTC is responsible of the technical decisions, with meetings each four months. Formed by 2 members from each institution. No role conflicts with PMB functions described in the Management section. Introduction of the Project Technical Committee in the Project Management Structure

59. Conclusions FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011 The objectives of the TRAMS project have a continued relevance with respect to the scientific state of the art and industrial requirements. The utilized resources agree with the planned and the achieved progress A set of minor modifications (task and deliverable title and date changes) has been proposed for the 3 years, the result is a smoother project flux. TRAMS objectives are key in the development of aggressively scaled systems beyond 2020. The proposed v&r solutions will enable integrated circuit progress to continue.

60. FIRST YEAR PROJECT REVIEW MEETING Leuven, April 12 th 2011