Designing a Single Cycle Datapath In this lecture, slides from lectures 3, 8 and 9 from the course Computer Architecture ECE 201 by Professor Mike Schulte.

Designing a Single Cycle Datapath In this lecture, slides from lectures 3, 8 and 9 from the course Computer Architecture ECE 201 by Professor Mike Schulte are used with permission. Computer Architecture ECE 201

The Big Picture: Where are We Now? °The Five Classic Components of a Computer °Today’s Topic: Design a Single Cycle Processor Control Datapath Memory Processor Input Output

The Big Picture: The Performance Perspective °Performance of a machine is determined by: Instruction count Clock cycle time Clock cycles per instruction °Processor design (datapath and control) will determine: Clock cycle time Clock cycles per instruction °Single cycle processor - one clock cycle per instruction Advantages: Simple design, low CPI Disadvantages: Long cycle time, which is limited by the slowest instruction. CPI Inst. CountCycle Time

How to Design a Processor: step-by-step 1. Analyze instruction set => datapath requirements the meaning of each instruction is given by register transfers R[rd] <– R[rs] + R[rt]; datapath must include storage element for ISA registers datapath must support each register transfer 2. Select set of datapath components and establish clocking methodology 3. Design datapath to meet the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Design the control logic

MIPS Instruction set

Review: The MIPS Instruction Formats °All MIPS instructions are 32 bits long. The three instruction formats are: R-type I-type J-type °The different fields are: op: operation of the instruction rs, rt, rd: the source and destination register specifiers shamt: shift amount funct: selects the variant of the operation in the “op” field address / immediate: address offset or immediate value target address: target address of the jump instruction optarget address 02631 6 bits26 bits oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrt immediate 016212631 6 bits16 bits5 bits

Translating MIPS Assembly into Machine Language °Humans see instructions as words (assembly language), but the computer sees them as ones and zeros (machine language). °An assembler translates from assembly language to machine language. °For example, the MIPS instruction add $t0, $s1, $s2 is translated as follows (see back of book): AssemblyComment addop = 0, shamt = 0, funct = 32 $t0rd = 8 $s1rs = 17 $s2rt = 18 00000100000 functshamt 01000 rd 10010 rt 10001 rs 000000 op

MIPS Addressing Modes °Addressing modes specify where the data used by an instruction is located. mode exampleaction register directadd $s1, $s2, $s3$s1  $s2 + $s3 immediateaddi $s1, $s2, 200$s1 = $s2 + 200 base+indexlw $s1, 200($s2)$s1 = mem[200 + $s2] PC-relativebeq $s1, $s2, 200if ($s1 == $s2) PC = PC+4+200*4 Pseudo-directj 4000PC = (PC[31:28], 4000*4) °Often, the type of addressing mode depends on the type of operation being performed (e.g., branches all use PC relative) °A summary of MIPS addressing modes is given on the back cover of the book.

MIPS Addressing Modes/Instruction Formats oprsrtrd immed register Register (direct) oprsrt register Base+index + Memory immedoprsrt Immediate immedoprsrt PC PC-relative + Memory All MIPS instructions are 32 bits wide - fixed length add $s1, $s2, $s3 addi $s1, $s2, 200 lw $s1, 200($s2) beq $s1, $s2, 200

Step 1a: The MIPS Subset for Today °ADD and SUB addu rd, rs, rt subu rd, rs, rt °OR Immediate: ori rt, rs, imm16 °LOAD and STORE lw rt, rs, imm16 sw rt, rs, imm16 °BRANCH: beq rs, rt, imm16 oprsrtrdshamtfunct 061116212631 6 bits 5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits oprsrtimmediate 016212631 6 bits16 bits5 bits

Register Transfer Logic (RTL) °RTL gives the meaning of the instructions °All instructions start by fetching the instruction op | rs | rt | rd | shamt | funct = MEM[ PC ] op | rs | rt | Imm16 = MEM[ PC ] inst Register Transfers adduR[rd] <– R[rs] + R[rt];PC <– PC + 4 subuR[rd] <– R[rs] – R[rt];PC <– PC + 4 oriR[rt] <– R[rs] + zero_ext(imm16); PC <– PC + 4 loadR[rt] <– MEM[ R[rs] + sign_ext(imm16)];PC <– PC + 4 storeMEM[ R[rs] + sign_ext(imm16) ] <– R[rt];PC <– PC + 4 beq if ( R[rs] == R[rt] ) then PC <– PC + 4 + sign_ext(imm16)] || 00 else PC <– PC + 4

Step 1: Requirements of the Instruction Set °Memory instruction & data °Registers (32 x 32) read rs read rt write rt or rd °PC °Extender (sign extend or zero extend) °Add and sub register or extended immediate °Add 4 or shifted extended immediate to PC

°Adder °MUX °ALU 32 A B Sum Carry 32 A B Result OP 32 A B Y Select Adder MUX ALU CarryIn 3 Step 2: Components of the Datapath Combinational Logic: Does not use a clock

Storage Element: Register (Basic Building Blocks) °Register Similar to the D Flip Flop except -N-bit input and output -Write enable input Write Enable: -negated (0): Data Out will not change -asserted (1): Data Out will become Data In on the falling edge of the clock Clk Data In Write Enable NN Data Out

Clocking Methodology - Negative Edge Triggered °All storage elements are clocked by the same clock edge °Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew Clk Don’t Care SetupHold........................ SetupHold

Storage Element: Register File °Register File consists of 32 registers: Two 32-bit output busses: busA and busB One 32-bit input bus: busW °Register is selected by: RA (number) selects the register to put on busA (data) RB (number) selects the register to put on busB (data) RW (number) selects the register to be written via busW (data) when Write Enable is 1 °Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, behaves as a combinational logic block: -RA or RB valid => busA or busB valid after “access time.” Clk busW Write Enable 32 busA 32 busB 555 RWRARB 32 32-bit Registers

°Built using D flip-flops Register File - Read

Register File - write

Storage Element: Idealized Memory °Memory (idealized) One input bus: Data In One output bus: Data Out °Memory word is selected by: Address selects the word to put on Data Out Write Enable = 1: address selects the memory word to be written via the Data In bus °Clock input (CLK) The CLK input is a factor ONLY during write operation During read operation, memory behaves as a combinational logic block: -Address valid => Data Out valid after “access time.” Clk Data In Write Enable 32 DataOut Address 32

Step 3 °Register Transfer Requirements –> Datapath Design Instruction Fetch Decode instructions and Read Operands Execute Operation Write back the result

3a: Overview of the Instruction Fetch Unit °The common RTL operations Fetch the Instruction: mem[PC] Update the program counter: -Sequential Code: PC <- PC + 4 -Branch and Jump: PC <- “something else” 32 Instruction Word Address Instruction Memory PC Clk Next Address Logic

3b: Add & Subtract °R[rd] <- R[rs] op R[rt] Example: addu rd, rs, rt Ra, Rb, and Rw come from instruction’s rs, rt, and rd fields ALUctr and RegWr: control logic after decoding the instruction 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers RsRtRd ALU oprsrtrdshamtfunct 061116212631 6 bits 5 bits 3

3c: Logical Operations with Immediate °R[rt] <- R[rs] op ZeroExt[imm16] Example : ori rt, rs, imm16 32 Result ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs RtRd RegDst ZeroExt Mux 32 16 imm16 ALUSrc ALU 11 oprsrtimmediate 016212631 6 bits16 bits5 bits rd? immediate 0161531 16 bits 0 0 0 0 0 0 0 0 3

3d: Load Operations °R[rt] <- Mem[R[rs] + SignExt[imm16]] Example: lw rt, rs, imm16 11 oprsrtimmediate 016212631 6 bits16 bits5 bits rd 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs RtRd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory 32 ALU MemWr Mux W_Src 3

3e: Store Operations °Mem[ R[rs] + SignExt[imm16] <- R[rt] ] Example: sw rt, rs, imm16 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Clk Data In WrEn 32 Adr Data Memory MemWr ALU oprsrtimmediate 016212631 6 bits16 bits5 bits 32 Mux W_Src 3

3f: The Branch Instruction °beqrs, rt, imm16 mem[PC]Fetch the instruction from memory Equal <- R[rs] == R[rt]Calculate the branch condition if (COND eq 0)Calculate the next instruction’s address -PC <- PC + 4 + ( SignExt(imm16) x 4 ) else -PC <- PC + 4 oprsrtimmediate 016212631 6 bits16 bits5 bits

Datapath for Branch Operations °beq rs, rt, imm16 Datapath generates condition (equal) oprsrtimmediate 016212631 6 bits16 bits5 bits 32 imm16 PC Clk 00 Adder Mux Adder 4 nPC_sel Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Equal? Cond PC Ext Inst Address

Putting it All Together: A Single Cycle Datapath imm16 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal Instruction 0 1 0 1 0 1 Imm16RdRtRs = Adder PC Clk 00 Mux 4 nPC_sel PC Ext Adr Inst Memory 3

Step 4: Given Datapath: RTL -> Control ALUctr RegDst ALUSrc ExtOp MemtoRegMemWr Equal Instruction Imm16RdRsRt nPC_sel Adr Inst Memory DATA PATH Control Op Fun RegWr

A Single Cycle Datapath °We have everything except control signals (underlined) Today’s lecture will look at how to generate the control signals

Meaning of the Control Signals °ExtOp:“zero”, “sign” °ALUsrc:0 => regB; 1 => immed °ALUctr:“add”, “sub”, “or” 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory MemWr ALU Equal 0 1 0 1 0 1 °MemWr:write memory °MemtoReg:0 => ALU; 1 => Mem °RegDst:0 => “rt”; 1 => “rd” °RegWr:write dest register = 3

RTL: The Add Instruction °addrd, rs, rt mem[PC]Fetch the instruction from memory R[rd] <- R[rs] + R[rt]The actual operation PC <- PC + 4Calculate the next instruction’s address oprsrtrdshamtfunct 061116212631 6 bits 5 bits

The Single Cycle Datapath during Add/Sub 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = 1 Extender Mux 32 16 imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rd] <- R[rs] op R[rt] 0 1 0 1 01 Imm16RdRsRt oprsrtrdshamtfunct 061116212631 nPC_sel= +4

Instruction Fetch Unit at the End of Add °PC <- PC + 4 This is the same for all instructions except Branch and Jump Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel = +4 imm16 Instruction

The Single Cycle Datapath during Or Immediate 32 ALUctr = Or Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = 0 Extender Mux 32 16 imm16 ALUSrc = 1 ExtOp = 0 Mux MemtoReg = 0 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction °R[rt] <- R[rs] or ZeroExt[Imm16] 0 1 0 1 01 Imm16RdRsRt oprsrtimmediate 016212631 nPC_sel= +4

The Single Cycle Datapath during Load 32 ALUctr = Add Clk busW RegWr = 1 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = 0 Extender Mux 32 16 imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = 1 Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt °R[rt] <- Data Memory {R[rs] + SignExt[imm16]} oprsrtimmediate 016212631 nPC_sel= +4

The Single Cycle Datapath during Store 32 ALUctr = Add Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = x Extender Mux 32 16 imm16 ALUSrc = 1 ExtOp = 1 Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 1 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt °Data Memory {R[rs] + SignExt[imm16]} <- R[rt] oprsrtimmediate 016212631 nPC_sel= +4

The Single Cycle Datapath during Branch 32 ALUctr = Subtract Clk busW RegWr = 0 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst = x Extender Mux 32 16 imm16 ALUSrc = 0 ExtOp = x Mux MemtoReg = x Clk Data In WrEn 32 Adr Data Memory 32 MemWr = 0 ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt °if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0 oprsrtimmediate 016212631 nPC_sel= “Br”

Instruction Fetch Unit at the End of Branch °if (Zero == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4 oprsrtimmediate 016212631 Adr Inst Memory Adder PC Clk 00 Mux 4 nPC_sel imm16 Instruction See book for what the datapath and control looks like for jump instructions. Compared to book our processor also supports the ORI instructions.

A Summary of the Control Signals addsuborilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite nPCsel Jump ExtOp ALUctr 1 0 0 1 0 0 0 x Add 1 0 0 1 0 0 0 x Subtract 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Subtract x x x 0 0 0 1 x xxx optarget address oprsrtrdshamtfunct 061116212631 oprsrt immediate R-type I-type J-type add, sub ori, lw, sw, beq jump func op00 0000 00 110110 001110 101100 010000 0010 Appendix A 10 0000See10 0010We Don’t Care :-)

Step 5: The Concept of Local Decoding Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 ALU

The Encoding of ALUop °In this exercise, ALUop has to be N=2 bits wide to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: -(2) Or, (3) Add, and (4) Subtract °To implement the full MIPS ISA, ALUop has to be 3 bits to represent: (1) “R-type” instructions “I-type” instructions that require the ALU to perform: -(2) Or, (3) Add, (4) Subtract (5) And (6) Set on < Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx

The Decoding of the “func” Field R-typeorilwswbeqjump ALUop (Symbolic)“R-type”OrAdd Subtract xxx ALUop 1 000 100 00 0 01 xxx Main Control op 6 ALU Control (Local) func N 6 ALUop ALUctr 3 oprsrtrdshamtfunct 061116212631 R-type funct Instruction Operation 10 0000 10 0010 10 0100 10 0101 10 1010 add subtract and or set-on-less-than ALUctr ALU Operation 000 001 010 110 111 Add Subtract And Or Set-on-less-than Get func from back of book for R-type Our processor only implements subset of operations

The Truth Table for ALUctr R-typeorilwswbeq ALUop (Symbolic) “R-type”OrAdd Subtract ALUop 1 000 100 00 0 01 funct Instruction Op. 0000 0010 0100 0101 1010 add subtract and or set-on-less-than This control is for more R-type instructions than our processor, but fewer than the entire MIPS ISA.

The Logic Equation for ALUctr ALUopfunc bit ALUctr 0x1xxxx1 1xx00101 1xx10101 °ALUctr = !ALUop & ALUop + ALUop & func

The Truth Table for ALUctr

The Logic Equation for ALUctr ALUopfunc bit 000xxxx1 ALUctr 0x1xxxx1 1xx00001 1xx00101 1xx10101 °ALUctr = !ALUop & !ALUop + ALUop & func

The Truth Table for ALUctr

The Logic Equation for ALUctr ALUopfunc bit ALUctr 01xxxxx1 1xx01011 1xx10101 °ALUctr = !ALUop & ALUop + ALUop & func & func + ALUop & func

The ALU Control Block ALU Control (Local) func 3 6 ALUop ALUctr 3 °ALUctr = !ALUop & ALUop + ALUop & func °ALUctr = !ALUop & !ALUop + ALUop & func °ALUctr = !ALUop & ALUop + ALUop & func & func + ALUop & func

The “Truth Table” for the Main Control R-typeorilwswbeqjump RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop (Symbolic) 1 0 0 1 0 0 0 x “R-type” 0 1 0 1 0 0 0 0 Or 0 1 1 1 0 0 0 1 Add x 1 x 0 1 0 0 1 x 0 x 0 0 1 0 x Subtract x x x 0 0 0 1 x xxx op00 000000 110110 001110 101100 010000 0010 ALUop 1000 0 x 0100 0 x 0000 1 x Main Control op 6 ALU Control (Local) func 3 6 ALUop ALUctr 3 RegDst ALUSrc :

The “Truth Table” for RegWrite R-typeorilwswbeqjump RegWrite111000 op00 000000 110110 001110 101100 010000 0010 °RegWrite = R-type + ori + lw = !op & !op & !op & !op & !op & !op (R-type) + !op & !op & op & op & !op & op (ori) + op & !op & !op & !op & op & op (lw) RegWrite

PLA Implementation of the Main Control RegWrite ALUSrc MemtoReg MemWrite Branch Jump RegDst ExtOp ALUop

Putting it All Together: A Single Cycle Processor 32 ALUctr Clk busW RegWr 32 busA 32 busB 555 RwRaRb 32 32-bit Registers Rs Rt Rd RegDst Extender Mux 32 16 imm16 ALUSrc ExtOp Mux MemtoReg Clk Data In WrEn 32 Adr Data Memory 32 MemWr ALU Instruction Fetch Unit Clk Zero Instruction 0 1 0 1 01 Imm16RdRsRt Main Control op 6 ALU Control func 6 3 ALUop ALUctr 3 RegDst ALUSrc : Instr nPC_sel

An abstract view of the critical path - load instruction Critical Path (Load Operation) = PC’s Clk-to-Q + Instruction Memory’s Access Time + Register File’s Access Time + ALU to Perform a 32-bit Add + Data Memory Access Time + Setup Time for Register File Write + Clock Skew Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 16 Imm 32 A B Next Address Worst case delay for load is much longer than needed for all other instructions, yet this sets the cycle time.

An Abstract View of the Implementation °Logical vs. Physical Structure Data Out Clk 5 RwRaRb 32 32-bit Registers Rd ALU Clk Data In Data Address Ideal Data Memory Instruction Address Ideal Instruction Memory Clk PC 5 Rs 5 Rt 32 A B Next Address Control Datapath Control Signals Conditions

Summary °5 steps to design a processor 1. Analyze instruction set => datapath requirements 2. Select set of datapath components & establish clock methodology 3. Design datapath meeting the requirements 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer. 5. Design the control logic °MIPS makes it easier Instructions same size Source registers always in same place Immediates same size, location Operations always on registers/immediates °Single cycle datapath => CPI=1, CCT => long °Next time: implementing control

Designing a Single Cycle Datapath In this lecture, slides from lectures 3, 8 and 9 from the course Computer Architecture ECE 201 by Professor Mike Schulte.

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Designing a Single Cycle Datapath In this lecture, slides from lectures 3, 8 and 9 from the course Computer Architecture ECE 201 by Professor Mike Schulte.

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Presentation on theme: "Designing a Single Cycle Datapath In this lecture, slides from lectures 3, 8 and 9 from the course Computer Architecture ECE 201 by Professor Mike Schulte."— Presentation transcript:

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