1. A First Look at the June Test Beam DAQ Hardware architecture Talk Presented 8 April, 2008 John Anderson HEP Electronics Group Argonne National Laboratory

2. 2 General Design of Test Beam Hardware The test beam setup will consist of up to four microchannel plate tubes (MCPs), each of which is connected to a constant-fraction discriminator (CFD). The CFD feeds a time-to-amplitude converter (TAC, Ortec 556) whose output is connected to an ADC (Ortec 114). –This setup is the same as previously used at ANL, LBL and other labs. –The timing error contribution attributable solely to the electronics is on the order of 3-4psec RMS. –The TAC at maximum resolution has a time range of 50ns and the ADC provides 14-bit resolution. This sets the LSB of the ADC to 3psec. The MTEST facility at Fermilab provides racks with trigger logic and has a CAMAC readout system already available. The CAMAC system is set up with the LeCroy FERA controllers that allow FERA-compatible devices to be read out at faster-than-CAMAC speeds. –The Ortec AD114 ADCs chosen for the test beam have FERA readout capability –Hardware has been obtained from FNAL and readout is being tested at ANL to insure fast setup. –FERA readout is fast enough to investigate rate effects in MCPs at ANL.

3. 3 The Basic Picture Engineer’s concept sketch – would really appreciate input from the scientists in the group!

4. 4 General Measurement Observations The MCPs are assumed to run in pairs for differential measurements. Delay cables are likely necessary between the CFDs and the TACs to insure that the Start and the Stop occur within 50ns of each other. The event rate is determined by ADC conversion time (5us) plus TAC output delay time (~1us) plus FERA readout time (~100ns/word, event size ~10 words/event). Allowing for additional systemic delays, 10kHz is a good guess. The scaler as shown does not participate in the readout of every event over the FERA bus; it is only for sanity checking “every so often”. As such its utility is limited. The MTEST setup provides TDCs used with wire chambers to provide further beam position information. These are not shown but if used would be read out over the same FERA bus. The 4302 memory depth is 16K words. Assuming a 10kHz event rate and 10 words per event, each 4302 will fill and be emptied multiple times during a spill of 1 second. –Readout over CAMAC (2us/word plus overhead) will create significant dead time. Expect at least 50%.

5. 5 Timing Considerations Propagation time of beam across the setup will be a few tens of nanoseconds, and generation of scintillator coincidence will take a few tens of ns more. –Inserting ~32ns delay cables between CFD output and TAC will insure that TAC Start & Stop are within 50ns of each other. Common start or common stop? –TAC auto-resets after ~1us if no STOP received after START, so system can be run either way; most people would use scintillator coincidence as common STOP –Could consider using coincidence to veto CFD outputs to minimize bad events (non-coincident MCP hits) since we have to delay CFD outputs anyway TAC has output delay >=500ns after STOP ADC has built-in discriminator, begins conversion when it sees an input transition of sufficient amplitude (self-gating). –External GATE input available if noise rate objectionable

6. 6 System Data Readout All ADC data will buffer up into one or more LeCroy 4302 CAMAC memories. –Each memory is 16K words, each event is a few words long –How much TDC data do we need per event? A existing readout program takes the data from the CAMAC memories into a PC. The DAQ program at MTEST does not “know” about the Ortec ADCs. –Ed May (ANL scientist) has been asked to assist the test beam effort on the software side –Effort is required well in advance of the test beam to insure that the DAQ works with all the hardware we plan to use Desirable to use same programming framework (and code) at both ANL and MTEST – requires easy switching from JY411 to CC-USB interface and drivers. – Evaluate, modify, use existing DAQ software and hardware at MTEST.

7. 7 Alignment Questions Presumably for best timing we plan to read out single anodes from MCP tubes –Who has responsibility for manufacturing dark enclosures for the MCP tubes for use at the test beam? –Are we using the exact same tube type in each station? Are we concerned about the beam spot size? –Will we need collimators? –Is all testing based on using Cherenkov light or do we expect direct charge deposition? Since measurements are differential between two MCP tubes, do we have sufficient mechanical movement precision to create picosecond (<15mil) stepping? How do we verify alignment while beam is running? Use an oscilloscope with external control of the staging tables?

8. 8 Testing at ANL ANL has received a loan of two FERA readout controllers, two CAMAC memories and two 3377 TDCs –John Anderson & Camden Ertley have successfully read out the Ortec ADC into the FERA memory and read data from the memory in a test setup; takes events at 200kHz. –Ed May is working to get the USB crate controllers we use here to work under Linux as a step towards porting the MTEST DAQ to ANL hardware –Next step is to integrate this hardware into the laser lab at ANL to make “dry run” of test beam setup to obtain baseline MCP data

9. 9 Open Questions that need answers Who has responsibility for data quality checking and analysis? Who has responsibility for working with the engineers to make sure the hardware setup is what is really desired? Who has responsibility for mechanical issues like dark enclosures and alignment? Who has responsibility for insuring the MCP tubes are correctly set up for beam use as opposed to laser stimulation? Who is making sure this all gets done in time?