1. CS/EE 5810 CS/EE 6810 F00: 1 Extracting More ILP

2. CS/EE 5810 CS/EE 6810 F00: 2 Going Beyond CPI=1 Two approaches for multiple-issue Superscalar –Issue varying number of instructions per clock »Constrained by structural hazards –scheduling »Static, by compiler »Dynamic, hardware support for some form of scoreboarding VLIW (Very Long Instruction Word) –Long instruction contains several real instructions –Hence need to be scheduled statically Int/brInt/Ld-StFP +/-FP mul/div

3. CS/EE 5810 CS/EE 6810 F00: 3 Superscalar DLX Superscalar DLX looks a lot like HP-PCXT (a.k.a. 7100) There are LOTS of complications even for a 2-way machine –Which instructions can issue together? (they must be independent) –How do you keep the decoding simple enough? »We now have to deal with 64bits for the 2 instructions »Could require instructions to be paired and aligned on a double-word boundary (Keeps pair in a cache line - 7100 had a 4-word Icache line size) »Also require that the int is first in the pair, avoids dynamic swapping of instructions –Result is that FP can only issue if the INT does…

4. CS/EE 5810 CS/EE 6810 F00: 4 Superscalar DLX Superscalar DLX: 2 instructions, 1 FP & 1 anything else – Fetch 64-bits/clock cycle; Int on left, FP on right – Can only issue 2nd instruction if 1st instruction issues – More ports for FP registers to do FP load & FP op in a pair TypePipeStages Int. instructionIFIDEXMEMWB FP instructionIFIDEXMEMWB Int. instructionIFIDEXMEMWB FP instructionIFIDEXMEMWB Int. instructionIFIDEXMEMWB FP instructionIFIDEXMEMWB 1 cycle load delay expands to 3 instructions in SS –instruction in right half can’t use it, nor instructions in next slot

5. CS/EE 5810 CS/EE 6810 F00: 5 Seem Simple? Registers –Each pipe now has its own set »Due to separation of int and FP instructions »Also separates data dependencies into two classes –There are exceptions… LDD, LDF for example »EFA is an integer operation »Destination register is in FP reg FP pipe has longer latency than int –Result is that completion is out of order »Complicates hazard control –Can pipeline FP alu, or provide multiple ALUs »In practice, many machines do both…

6. CS/EE 5810 CS/EE 6810 F00: 6 Review: Unrolled Loop that Minimizes Stalls for Scalar 1 Loop:LDF0,0(R1) 2 LDF6,-8(R1) 3 LDF10,-16(R1) 4 LDF14,-24(R1) 5 ADDDF4,F0,F2 6 ADDDF8,F6,F2 7 ADDDF12,F10,F2 8 ADDDF16,F14,F2 9 SD0(R1),F4 10 SD-8(R1),F8 11 SD-16(R1),F12 12 SUBIR1,R1,#32 13 BNEZR1,LOOP 14 SD8(R1),F16; 8-32 = -24 14 clock cycles, or 3.5 per iteration LD to ADDD: 1 Cycle ADDD to SD: 2 Cycles

7. CS/EE 5810 CS/EE 6810 F00: 7 Loop Unrolling in Superscalar Integer instructionFP instructionClock cycle Loop:LD F0,0(R1)1 LD F6,-8(R1)2 LD F10,-16(R1)ADDD F4,F0,F23 LD F14,-24(R1)ADDD F8,F6,F24 LD F18,-32(R1)ADDD F12,F10,F25 SD 0(R1),F4ADDD F16,F14,F26 SD -8(R1),F8ADDD F20,F18,F27 SD -16(R1),F128 SD -24(R1),F169 SUBI R1,R1,#4010 BNEZ R1,LOOP11 SD -32(R1),F2012 Unrolled 5 times to avoid delays (+1 due to SS) 12 clocks, or 2.4 clocks per iteration (1.5X)

8. CS/EE 5810 CS/EE 6810 F00: 8 Multiple Issue Challenges While Integer/FP split is simple for the HW, get CPI of 0.5 only for programs with: –Exactly 50% FP operations –No hazards If more instructions issue at same time, greater difficulty of decode and issue –Even 2-scalar => examine 2 opcodes, 6 register specifiers, & decide if 1 or 2 instructions can issue VLIW: tradeoff instruction space for simple decoding –The long instruction word has room for many operations –By definition, all the operations the compiler puts in the long instruction word are independent => execute in parallel –E.g., 2 integer operations, 2 FP ops, 2 Memory refs, 1 branch »16 to 24 bits per field => 7*16 or 112 bits to 7*24 or 168 bits wide –Need compiling technique that schedules across several branches –Code size may go up - you need to fill the empty slots with NOP

9. CS/EE 5810 CS/EE 6810 F00: 9 Superscalar in Practice? Test example - scalar-vector sum –Shows 50% improvement over scheduled single-issue HP7100 experience –Getting simple 2-way issue right is not too hard –Most applications show 50%-70% speedup –No applications slow down »However, very branchy code doesn’t speed up much –What did slow down? »The compiler! Increased compiler complexity… Still, basically a win –Got 1/2 to 3/4 of the idea speedup –Too bad the benefits diminish with increased issue width…

10. CS/EE 5810 CS/EE 6810 F00: 10 VLIW History Snippet Go back to the early 80’s… Cyndrome –Bob Rau - VLIW compiler guy from U of Illinois is chief architect Multiflow –Josh Fisher - VLIW compiler guy from Yale is chief architect Both went after the mini-supercomputer market –mini-super = Cray-like performance for a lot less money –Market segment disappeared before machines were ready Rau and Fisher both went to work for HP –HP develops PA-WW and then forms partnership with Intel Result is the VLIW Merced (Itainium, IA-64, EPIC)

11. CS/EE 5810 CS/EE 6810 F00: 11 Intel/HP “Explicitly Parallel Instruction Computer (EPIC)” 3 Instructions in 128 bit “groups”; field determines if instructions dependent or independent –Smaller code size than old VLIW, larger than x86/RISC –Groups can be linked to show independence > 3 instr 64 integer registers + 64 floating point registers –Not separate files per functional unit as in old VLIW Hardware checks dependencies (interlocks => binary compatibility over time) Predicated execution (select 1 out of 64 1-bit flags) => 40% fewer mispredictions? IA-64 : name of instruction set architecture; EPIC is type Merced is internal name of first implementation (1999) Itainium it the name of the first chip you can buy

12. CS/EE 5810 CS/EE 6810 F00: 12 Loop Unrolling in VLIW Memory MemoryFPFPInt. op/Clock reference 1reference 2operation 1 op. 2 branch LD F0,0(R1)LD F6,-8(R1)1 LD F10,-16(R1)LD F14,-24(R1)2 LD F18,-32(R1)LD F22,-40(R1)ADDD F4,F0,F2ADDD F8,F6,F23 LD F26,-48(R1)ADDD F12,F10,F2ADDD F16,F14,F24 ADDD F20,F18,F2ADDD F24,F22,F25 SD 0(R1),F4SD -8(R1),F8ADDD F28,F26,F26 SD -16(R1),F12SD -24(R1),F167 SD -32(R1),F20SD -40(R1),F24SUBI R1,R1,#488 SD -0(R1),F28BNEZ R1,LOOP9 Unrolled 7 times to avoid delays 7 results in 9 clocks, or 1.3 clocks per iteration (1.8X) Average: 2.5 ops per clock, 50% efficiency Note: Need more registers in VLIW (15 vs. 6 in SS)

13. CS/EE 5810 CS/EE 6810 F00: 13 Advantages of HW (Tomasulo) vs. SW (VLIW) Speculation HW determines address conflicts HW better branch prediction HW maintains precise exception model HW does not execute bookkeeping instructions Works across multiple implementations SW speculation is much easier for HW design

14. CS/EE 5810 CS/EE 6810 F00: 14 Superscalar v. VLIW Smaller code size Binary compatability across generations of hardware Simplified Hardware for decoding, issuing instructions No Interlock Hardware (compiler checks?) More registers, but simplified Hardware for Register Ports (multiple independent register files?)

15. CS/EE 5810 CS/EE 6810 F00: 15 Multi-Issue Dynamic Scheduling Scoreboarding required –Let’s pick dataflow model = Tomasulo –Issue and let the reservation stations sort things our –But, still can’t issue a dependent pair on the same cycle 2 options for fixing the dependent pair problem –Pipeline the IF/ID stage and run twice as fast as EX »Not too hard since IF and ID are pretty simple »Not true for CISC like X86 –Decoupling »Provide queues for destinations of loads, moves, stores »Sort of virtual-register/renaming approach »Scoreboard will become more complex »But performance will likely go up

16. CS/EE 5810 CS/EE 6810 F00: 16 Dynamic Scheduling in Superscalar How to issue two instructions and keep in-order instruction issue for Tomasulo? –Assume 1 integer + 1 floating point –1 Tomasulo control for integer, 1 for floating point Issue 2X Clock Rate, so that issue remains in order Only FP loads might cause dependency between integer and FP issue: –Replace load reservation station with a load queue; operands must be read in the order they are fetched –Load checks addresses in Store Queue to avoid RAW violation –Store checks addresses in Load Queue to avoid WAR,WAW –Called “decoupled architecture”

17. CS/EE 5810 CS/EE 6810 F00: 17 Performance of Dynamic SS Iteration InstructionsIssues ExecutesWrites result no. clock-cycle number 1LD F0,0(R1)124 1ADDD F4,F0,F2158 1SD 0(R1),F429 1SUBI R1,R1,#8345 1BNEZ R1,LOOP45 2LD F0,0(R1)568 2ADDD F4,F0,F25912 2SD 0(R1),F4613 2SUBI R1,R1,#8789 2BNEZ R1,LOOP89 ­ 4 clocks per iteration; only 1 FP instr/iteration Branches, Decrements issues still take 1 clock cycle How get more performance?

18. CS/EE 5810 CS/EE 6810 F00: 18 Software Pipelining Observation: if iterations from loops are independent, then can get more ILP by taking instructions from different iterations Software pipelining: reorganizes loops so that each iteration is made from instructions chosen from different iterations of the original loop (­ Tomasulo in SW)

19. Software Pipelining Example Before: Unrolled 3 times 1 LDF0,0(R1) 2 ADDDF4,F0,F2 3 SD0(R1),F4 4 LDF6,-8(R1) 5 ADDDF8,F6,F2 6 SD-8(R1),F8 7 LDF10,-16(R1) 8 ADDDF12,F10,F2 9 SD-16(R1),F12 10 SUBIR1,R1,#24 11 BNEZR1,LOOP After: Software Pipelined 1 SD0(R1),F4 ;Stores M[i] 2 ADDDF4,F0,F2 ;Adds to M[i-1] 3 LDF0,-16(R1);Loads M[i-2] 4 SUBIR1,R1,#8 5 BNEZR1,LOOP Symbolic Loop Unrolling – Maximize result-use distance – Less code space than unrolling – Fill & drain pipe only once per loop vs. once per each unrolled iteration in loop unrolling SW Pipeline Loop Unrolled overlapped ops Time

20. CS/EE 5810 CS/EE 6810 F00: 20 Trace Scheduling Parallelism across IF branches vs. LOOP branches Two steps: –Trace Selection »Find likely sequence of basic blocks (trace) of (statically predicted or profile predicted) long sequence of straight-line code –Trace Compaction »Squeeze trace into few VLIW instructions »Need bookkeeping code in case prediction is wrong Compiler undoes bad guess (discards values in registers) Subtle compiler bugs mean wrong answer vs. poor performance; no hardware interlocks

21. CS/EE 5810 CS/EE 6810 F00: 21 Limitations on Multiple Issue How much ILP can be found in the application –Most fundamental problem –Requires deep unrolling, hence big focus on loops »Compiler complexity goes way up »Deep unrolling requires lots of registers (either real or renamed) –Increased HW cost »More ports for RF »Cost of scoreboarding and forwarding paths »Memory bandwidth goes way up - the biggie! »Most machines have separate I and D ports already »Some even have multiple D ports, big expense! »Branch prediction HW is a MUST

22. CS/EE 5810 CS/EE 6810 F00: 22 Limits to Multi-Issue Machines Inherent limitations of ILP –1 branch in 5: How to keep a 5-way VLIW busy? –Latencies of units: many operations must be scheduled –Need about Pipeline Depth x No. Functional Units of independentDifficulties in building HW –Easy: More instruction bandwidth –Easy: Duplicate FUs to get parallel execution –Hard: Increase ports to Register File (bandwidth) »VLIW example needs 7 read and 3 write for Int. Reg. & 5 read and 3 write for FP reg –Harder: Increase ports to memory (bandwidth) –Decoding Superscalar and impact on clock rate, pipeline depth?

23. CS/EE 5810 CS/EE 6810 F00: 23 Limits to Multi-Issue Machines Limitations specific to either Superscalar or VLIW implementation –Decode issue in Superscalar: how wide practical? –VLIW code size: unroll loops + wasted fields in VLIW »IA-64 compresses dependent instructions, but still larger –VLIW lock step => 1 hazard & all instructions stall »IA-64 not lock step? Dynamic pipeline? –VLIW & binary compatibility - IA-64 promises binary compatibility

24. CS/EE 5810 CS/EE 6810 F00: 24 Limits to ILP Conflicting studies of amount –Benchmarks (vectorized Fortran FP vs. integer C programs) –Hardware sophistication –Compiler sophistication How much ILP is available using existing mechanims with increasing HW budgets? Do we need to invent new HW/SW mechanisms to keep on processor performance curve?

25. CS/EE 5810 CS/EE 6810 F00: 25 Limits to ILP Initial HW Model here; MIPS compilers. Assumptions for ideal/perfect machine to start: 1. Register renaming–infinite virtual registers and all WAW & WAR hazards are avoided 2. Branch prediction–perfect; no mispredictions 3. Jump prediction–all jumps perfectly predicted => machine with perfect speculation & an unbounded buffer of instructions available 4. Memory-address alias analysis–addresses are known & a store can be moved before a load provided addresses not equal 1 cycle latency for all instructions; unlimited number of instructions issued per clock cycle

26. CS/EE 5810 CS/EE 6810 F00: 26 Upper Limit to ILP: Ideal Machine (Figure 4.38, page 319) Integer: 18 - 60 FP: 75 - 150 IPC

27. Program Instruction issues per cycle 0 10 20 30 40 50 60 gccexpressolifppppdoducdtomcatv 63 18 73119150 10 15 12 49 16 10 13 11 35 15 34 8 8 14 44 9 5 9 23 44 6 55 3 3 33 45 22 Infinite5121283284 Effect of Window Size 005121283284 Figure 4.40 Page 323

28. More Realistic HW: Branch Impact Figure 4.42, Page 325 Change from Infinite window to examine to 2000 and maximum issue of 64 instructions per clock cycle ProfileBHT (512)Pick Cor. or BHTPerfect No prediction FP: 15 - 45 Integer: 6 - 12 IPC

29. More Realistic HW: Register Impact Figure 4.44, Page 328 Change 2000 instr window, 64 instr issue, 8K 2 level Prediction 64None256Infinite32128 Integer: 5 - 15 FP: 11 - 45 IPC

30. More Realistic HW: Alias Impact Figure 4.46, Page 330 Change 2000 instr window, 64 instr issue, 8K 2 level Prediction, 256 renaming registers None Global/Stack perfect Perfect Inspec. Assem. FP: 4 - 45 (Fortran, no heap) Integer: 4 - 9 IPC

31. Realistic HW for ‘9X: Window Impact (Figure 4.48, Page 332) Perfect disambiguation (HW), 1K Selective Prediction, 16 entry return, 64 registers, issue as many as window 6416256Infinite3212884 Integer: 6 - 12 FP: 8 - 45 IPC

32. CS/EE 5810 CS/EE 6810 F00: 32 How Realistic is This? 64 issue with no issue restrictions –Is this realistic? 64 memory references in one cycle? Hmmm… Selective predictor with 1k entries 16 entry return predictor Dynamic perfect memory disambiguation –Also a bit unlikely Register renaming with 64 additional FP regs and 64 additional int regs

33. CS/EE 5810 CS/EE 6810 F00: 33 Specs of Some Machines

34. CS/EE 5810 CS/EE 6810 F00: 34 3 1996 Era Machines Alpha 21164PProHP PA-8000 Year199519951996 Clock400 MHz200 MHz180 MHz Cache8K/8K/96K/2M8K/8K/0.5M0/0/2M Issue rate2int+2FP3 instr (x86)4 instr Pipe stages7-912-147-9 Out-of-Order6 loads40 instr (µop)56 instr Rename regsnone4056

35. CS/EE 5810 CS/EE 6810 F00: 35 Alpha 21164Pentium IIHP PA-8000 Year199519961996 Clock600 MHz (‘97)300 MHz (‘97) 236 MHz (‘97) Cache8K/8K/96K/2M16K/16K/0.5M0/0/4M Issue rate2int+2FP3 instr (x86)4 instr Pipe stages7-912-147-9 Out-of-Order6 loads40 instr (µop)56 instr Rename regsnone4056 3 1997 Era Machines

36. CS/EE 5810 CS/EE 6810 F00: 36 Summary Speculation: – Execution before control dependencies are resolved –Out-of-order execution, In-order commit (reorder buffer) SW Pipelining –Symbolic Loop Unrolling to get most from pipeline with little code expansion, little overhead Superscalar and VLIW: CPI 1) –Dynamic issue vs. Static issue –More instructions issue at same time => larger hazard penalty Hardware based speculation – dynamic branch prediction – speculation – dynamic scheduling