1. ECEN4533 Data Communications Lecture #3710 April 2013 Dr. George Scheets n Read 6.1 – 6.2 n Problems: Web 27 & 28 n Exam #2: < 15 April (DL) n Corrected Quizzes due u 10 April (Live) & 1 week after return (DL) n Corrected tests due 17 April (Live) n Design #2 Final Results u Hi = 80, Low = 43.8, Ave = 68.60, σ = 14.23

2. ECEN4533 Data Communications Lecture #3812 April 2013 Dr. George Scheets n Read 6.3 n Problems: 4.2, 4.8, Web 29 n Exam #2: < 15 April (DL) n Corrected Quizzes due 1 week after return (DL) n Corrected tests due 17 April (Live) n Wireshark Project due by midnight 4 May (All) u Late turn in NOT accepted u 15 points + 20 points extra credit

3. 2013 OSU ECE Spring Banquet n Hosted by Student Branch of IEEE n Wednesday, 17 April, at Meditations n Doors open at 5:30 pm, meal at 6:00 pm n Cash Bar n Sign up in ES202 to reserve your seat(s) n $5 a head (for a $16 meal!) u if pay in advance and resume submitted to OSUIEEEresume@gmail.com < noon, 16 April. Otherwise $8. n Speaker: Dr. Matt Perry Director, SiArch n Dress is Business Casual n Many door prizes available! +10 points extra credit n All are invited! Sponsored in part by:

4. Ways to decrease P(Bit Error) n Crank up power out n Reduce noise in system n Slow down transmitted bit rate n Use directional antennas u Need some fancy DSP to steer beams n Use Forward Error Correcting codes u Add controlled redundancy to bit stream u Extra parity bits must be transmitted F System at BW limit w/o FEC? Go M-Ary or reduce Layer 2-7 bps

5. No coding: Binary System Source Channel Channel Coder Symbol Detector n Source: Outputs a bit stream n Channel Coder: Maps bit stream into a form suitable for channel n Channel: Attenuates, distorts, & adds noise n Symbol Detector: Looks at received symbol and decides (if binary) "1?" or "0?" Suppose P(Bit Error) = 0.1

6. 2:1 FEC Binary System Source Source Coder: Input = 1 bit. Output = Input + Parity bit. Channel Channel Coder Symbol Detector Source Decoder: Looks at blocks of 2 bits. Outputs 1 bit. R bps Layer 2-7 2R coded bps 2R coded bps R bps n Suppose P(Coded BE) = 0.1 n P(Layer 2-7 BE) also = 0.1 *Binary → 2x BW *4-Ary → same BW 2 bits/symbol

7. Example) Two bit code words n Suppose you now transmit each bit twice, and P(Code Bit Error) =.1 u Legal Transmitted code words; 00, 11 u Possible received code words 00, 11 (appears legal, 0 or 2 bits decoded in error) 01, 10 (clearly illegal, 1 bit decoded in error) P(No bits in error) =.9*.9 =.81 P(One bit in error) = 2*.9*.1 =.18 P(Both bits in error) =.1*.1 =.01 u Decoder takes 2 Code bits at a time & outputs 1 bit of Data If illegal code word received, it can guess 0 or 1. 81% + 18%(1/2) = 90% of time the correct bit is output 1% + 18%(1/2) = 10% of time the incorrect bit is output u Same performance as No Coding @ twice the bit rate

8. 3:1 FEC Binary System Source Source Coder: Input = 1 bit. Output = Input + 2 Parity bits Channel Channel Coder Symbol Detector Source Decoder: Looks at blocks of 3 bits. Outputs 1 bit. R bps Layer 2-7 3R coded bps 3R coded bps R bps n Suppose P(Code BE) = 0.1 *Binary → 3x BW *8-Ary → same BW 3 bits/symbol

9. Example) SSD 3 bit code words n Transmit each bit thrice, P(Code Bit Error) =.1 u Legal Transmitted code words; 000, 111 u Possible received code words 000, 111 (appears legal, 0 or 3 bits in error) 001, 010, 100 (clearly illegal, 1 or 2 bits in error) 011, 101, 110 (clearly illegal, 1 or 2 bits in error) P(No bits in error) =.9*.9*.9 =.729 P(One bit in error) = 3*.9 2 *.1 =.243 P(Two bits in error) = 3*.9*.1 2 =.027 P(Three bits in error) =.1*.1*.1 =.001 u Decoder takes 3 bits at a time & outputs 1 bit. Majority Rules. 72.9% + 24.3% = 97.2% of time correct bit is output.1% + 2.7% = 2.8% of time incorrect bit is output u Improved performance as No Coding @ thrice the bit rate

10. Local Oscillator On Frequency & Phase X = Cos(0)

11. Local Oscillator off frequency X = Cos(2πΔf)

12. Doppler Effect 60 mph (26.8 m/sec), 2 m offset

13. Receiver Phase Locked Loop X Active Low Pass Filter Voltage Controlled Oscillator cosω c t (from antenna) sin((ω vco t +θ) -sin((ω vco -ω c )t+θ) VCO set to free run at ≈ ω c VCO output frequency = ω c + K * input voltage LPF with negative gain. 2 sinα cosβ = sin(α-β) + sin(α+β)

14. Phase Locked Loop X Active Low Pass Filter Voltage Controlled Oscillator cosω c t (from antenna) sin(ω vco t) -sin((ω vco -ω c )t) VCO frequency and phase locked. ω vco -ω c = 0 & θ = 0 Input to VCO = 0 volts. LPF with negative gain.

15. Phase Locked Loop X Active Low Pass Filter Voltage Controlled Oscillator cosω c t (from antenna) -sinθ VCO on frequency & positive θ? VCO phase is slightly ahead & needs to slow down. Negative voltage momentarily applied. sin((ω vco t )+θ) LPF with negative gain.

16. Phase Locked Loop X Active Low Pass Filter Voltage Controlled Oscillator cosω c t (from antenna) sinω vco t -sin(ω vco -ω c )t LPF with negative gain. VCO off frequency? Oscillating input voltage moves VCO frequency up & down. If close enough to input, system will lock.

17. M-Ary Signaling n One of M possible signals transmitted each symbol interval n Tends to be used where bandwidth is tight & SNR decent at the receiver. n Each symbol can represent log 2 (M) bits n Example: In 16 PSK u one of 16 possible phase angles is transmitted every symbol interval u each symbol can represent 4 bits n QAM normally used u each symbol has different amplitude & phase