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© David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 1 Programming Massively Parallel Processors Lecture.

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Presentation on theme: "© David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 1 Programming Massively Parallel Processors Lecture."— Presentation transcript:

1 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 1 Programming Massively Parallel Processors Lecture Slides for Chapter 8: Application Case Study – Advanced MRI Reconstruction

2 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 2 Objective To learn about computational thinking skills through a concrete example –Problem formulation –Designing implementations to steer around limitations –Validating results –Understanding the impact of your improvements A top to bottom experience!

3 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 3 Acknowledgements Sam S. Stone §, Haoran Yi §, Justin P. Haldar †, Deepthi Nandakumar, Bradley P. Sutton †, Zhi-Pei Liang †, Keith Thulburin* § Center for Reliable and High-Performance Computing † Beckman Institute for Advanced Science and Technology Department of Electrical and Computer Engineering University of Illinois at Urbana-Champaign * University of Illinois, Chicago Medical Center

4 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 4 Overview Magnetic resonance imaging Non-Cartesian Scanner Trajectory Least-squares (LS) reconstruction algorithm Optimizing the LS reconstruction on the G80 –Overcoming bottlenecks –Performance tuning Summary

5 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 5 Reconstructing MR Images Cartesian Scan DataSpiral Scan Data Gridding FFTLS 2 Cartesian scan data + FFT: Slow scan, fast reconstruction, images may be poor

6 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 6 Reconstructing MR Images Cartesian Scan DataSpiral Scan Data Gridding 1 FFTLS Spiral scan data + Gridding + FFT: Fast scan, fast reconstruction, better images 2 1 Based on Fig 1 of Lustig et al, Fast Spiral Fourier Transform for Iterative MR Image Reconstruction, IEEE Int’l Symp. on Biomedical Imaging, 2004

7 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 7 Reconstructing MR Images Cartesian Scan DataSpiral Scan Data Gridding FFTLeast-Squares (LS) Spiral scan data + LS Superior images at expense of significantly more computation 2

8 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 8 An Exciting Revolution - Sodium Map of the Brain Images of sodium in the brain –Very large number of samples for increased SNR –Requires high-quality reconstruction Enables study of brain-cell viability before anatomic changes occur in stroke and cancer treatment – within days! Courtesy of Keith Thulborn and Ian Atkinson, Center for MR Research, University of Illinois at Chicago

9 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 9 Least-Squares Reconstruction Compute Q for F H F Acquire Data Compute F H d Find ρ Q depends only on scanner configuration F H d depends on scan data ρ found using linear solver Accelerate Q and F H d on G80 –Q: 1-2 days on CPU –F H d: 6-7 hours on CPU –ρ: 1.5 minutes on CPU

10 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 10 for (m = 0; m < M; m++) { phiMag[m] = rPhi[m]*rPhi[m] + iPhi[m]*iPhi[m]; for (n = 0; n < N; n++) { expQ = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); rQ[n] +=phiMag[m]*cos(expQ); iQ[n] +=phiMag[m]*sin(expQ); } (a) Q computation for (m = 0; m < M; m++) { rMu[m] = rPhi[m]*rD[m] + iPhi[m]*iD[m]; iMu[m] = rPhi[m]*iD[m] – iPhi[m]*rD[m]; for (n = 0; n < N; n++) { expFhD = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); cArg = cos(expFhD); sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; } }(b) F H d computation Q v.s. F H D

11 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 11 for (m = 0; m < M; m++) { rMu[m] = rPhi[m]*rD[m] + iPhi[m]*iD[m]; iMu[m] = rPhi[m]*iD[m] – iPhi[m]*rD[m]; for (n = 0; n < N; n++) { expFhD = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); cArg = cos(expFhD); sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; } Algorithms to Accelerate Scan data –M = # scan points –kx, ky, kz = 3D scan data Pixel data –N = # pixels –x, y, z = input 3D pixel data –rFhD, iFhD= output pixel data Complexity is O(MN) Inner loop –13 FP MUL or ADD ops –2 FP trig ops –12 loads, 2 stores

12 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 12 From C to CUDA: Step 1 What unit of work is assigned to each thread? for (m = 0; m < M; m++) { rMu[m] = rPhi[m]*rD[m] + iPhi[m]*iD[m]; iMu[m] = rPhi[m]*iD[m] – iPhi[m]*rD[m]; for (n = 0; n < N; n++) { expFhD = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); cArg = cos(expFhD); sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; }

13 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 13 __global__ void cmpFHd(float* rPhi, iPhi, phiMag, kx, ky, kz, x, y, z, rMu, iMu, int N) { int m = blockIdx.x * FHD_THREADS_PER_BLOCK + threadIdx.x; rMu[m] = rPhi[m]*rD[m] + iPhi[m]*iD[m]; iMu[m] = rPhi[m]*iD[m] – iPhi[m]*rD[m]; for (n = 0; n < N; n++) { expFhD = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); cArg = cos(expFhD); sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; } One Possibility

14 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 14 __global__ void cmpFHd(float* rPhi, iPhi, phiMag, kx, ky, kz, x, y, z, rMu, iMu, int N) { int m = blockIdx.x * FHD_THREADS_PER_BLOCK + threadIdx.x; float rMu_reg, iMu_reg; rMu_reg = rMu[m] = rPhi[m]*rD[m] + iPhi[m]*iD[m]; iMu_reg = iMu[m] = rPhi[m]*iD[m] – iPhi[m]*rD[m]; for (n = 0; n < N; n++) { expFhD = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); cArg = cos(expFhD); sArg = sin(expFhD); rFhD[n] += rMu_reg*cArg – iMu_reg*sArg; iFhD[n] += iMu_reg*cArg + rMu_reg*sArg; } One Possibility - Improved

15 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 15 Back to the Drawing Board – Maybe map the n loop to threads? for (m = 0; m < M; m++) { rMu[m] = rPhi[m]*rD[m] + iPhi[m]*iD[m]; iMu[m] = rPhi[m]*iD[m] – iPhi[m]*rD[m]; for (n = 0; n < N; n++) { expFhD = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); cArg = cos(expFhD); sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; }

16 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 16 for (m = 0; m < M; m++) { rMu[m] = rPhi[m]*rD[m] + iPhi[m]*iD[m]; iMu[m] = rPhi[m]*iD[m] – iPhi[m]*rD[m]; for (n = 0; n < N; n++) { expFhD = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); cArg = cos(expFhD); sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; } (a) F H d computation for (m = 0; m < M; m++) { for (n = 0; n < N; n++) { rMu[m] = rPhi[m]*rD[m] + iPhi[m]*iD[m]; iMu[m] = rPhi[m]*iD[m] – iPhi[m]*rD[m]; expFhD = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); cArg = cos(expFhD); sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; } }(b) after code motion

17 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 17 __global__ void cmpFHd(float* rPhi, iPhi, phiMag, kx, ky, kz, x, y, z, rMu, iMu, int N) { int n = blockIdx.x * FHD_THREADS_PER_BLOCK + threadIdx.x; for (m = 0; m < M; m++) { float rMu_reg = rMu[m] = rPhi[m]*rD[m] + iPhi[m]*iD[m]; float iMu_reg = iMu[m] = rPhi[m]*iD[m] – iPhi[m]*rD[m]; float expFhD = 2*PI*(kx[m]*x[n]+ky[m]*y[n]+kz[m]*z[n]); float cArg = cos(expFhD); float sArg = sin(expFhD); rFhD[n] += rMu_reg*cArg – iMu_reg*sArg; iFhD[n] += iMu_reg*cArg + rMu_reg*sArg; } 6 A Second Option for the cmpFHd Kernel

18 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 18 We do have another option.

19 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 19 for (m = 0; m < M; m++) { rMu[m] = rPhi[m]*rD[m] + iPhi[m]*iD[m]; iMu[m] = rPhi[m]*iD[m] – iPhi[m]*rD[m]; for (n = 0; n < N; n++) { expFhD = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); cArg = cos(expFhD); sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; } (a) F H d computation for (m = 0; m < M; m++) { rMu[m] = rPhi[m]*rD[m] + iPhi[m]*iD[m]; iMu[m] = rPhi[m]*iD[m] – iPhi[m]*rD[m]; } for (m = 0; m < M; m++) { for (n = 0; n < N; n++) { expFhD = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); cArg = cos(expFhD); sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; } }(b) after loop fission

20 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 20 __global__ void cmpMu(float* rPhi, iPhi, rD, iD, rMu, iMu) { int m = blockIdx.x * MU_THREAEDS_PER_BLOCK + threadIdx.x; rMu[m] = rPhi[m]*rD[m] + iPhi[m]*iD[m]; iMu[m] = rPhi[m]*iD[m] – iPhi[m]*rD[m]; } A Separate cmpMu Kernel

21 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 21 __global__ void cmpFHd(float* rPhi, iPhi, phiMag, kx, ky, kz, x, y, z, rMu, iMu, int N) { int m = blockIdx.x * FHD_THREADS_PER_BLOCK + threadIdx.x; for (n = 0; n < N; n++) { float expFhD = 2*PI*(kx[m]*x[n]+ky[m]*y[n]+kz[m]*z[n]); float cArg = cos(expFhD); float sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; } 6

22 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 22 for (m = 0; m < M; m++) { for (n = 0; n < N; n++) { expFhD = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); cArg = cos(expFhD); sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; } } (a) before loop interchange for (n = 0; n < N; n++) { for (m = 0; m < M; m++) { expFhD = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]); cArg = cos(expFhD); sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; } } (b) after loop interchange Figure 7.9 Loop interchange of the F H D computation

23 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 23 __global__ void cmpFHd(float* rPhi, iPhi, phiMag, kx, ky, kz, x, y, z, rMu, iMu, int N) { int m = blockIdx.x * FHD_THREADS_PER_BLOCK + threadIdx.x; for (n = 0; n < N; n++) { float expFhD = 2*PI*(kx[m]*x[n]+ky[m]*y[n]+kz[m]*z[n]); float cArg = cos(expFhD); float sArg = sin(expFhD); rFhD[n] += rMu[m]*cArg – iMu[m]*sArg; iFhD[n] += iMu[m]*cArg + rMu[m]*sArg; } 6 A Third Option of FHd kernel

24 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 24 __global__ void cmpFHd(float* rPhi, iPhi, phiMag, kx, ky, kz, x, y, z, rMu, iMu, int M) { int n = blockIdx.x * FHD_THREADS_PER_BLOCK + threadIdx.x; float xn_r = x[n]; float yn_r = y[n]; float zn_r = z[n]; float rFhDn_r = rFhD[n]; float iFhDn_r = iFhD[n]; for (m = 0; m < M; m++) { float expFhD = 2*PI*(kx[m]*xn_r+ky[m]*yn_r+kz[m]*zn_r); float cArg = cos(expFhD); float sArg = sin(expFhD); rFhDn_r += rMu[m]*cArg – iMu[m]*sArg; iFhDn_r += iMu[m]*cArg + rMu[m]*sArg; } rFhD[n] = rFhD_r; iFhD[n] = iFhD_r; } Using Registers to Reduce Global Memory Traffic

25 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 25 Tiling of Scan Data LS recon uses multiple grids –Each grid operates on all pixels –Each grid operates on a distinct subset of scan data –Each thread in the same grid operates on a distinct pixel for (m = 0; m < M/32; m++) { exQ = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]) rQ[n] += phi[m]*cos(exQ) iQ[n] += phi[m]*sin(exQ) } 12 Thread n operates on pixel n:

26 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 26 __constant__ float kx_c[CHUNK_SIZE], ky_c[CHUNK_SIZE], kz_c[CHUNK_SIZE]; … __ void main() { int i; for (i = 0; i < M/CHUNK_SIZE; i++); cudaMemcpy(kx_c,&kx[i*CHUNK_SIZE],4*CHUNK_SIZE, cudaMemCpyHostToDevice); cudaMemcpy(ky_c,&ky[i*CHUNK_SIZE],4*CHUNK_SIZE, cudaMemCpyHostToDevice); … cmpFHD >> (rPhi, iPhi, phiMag, x, y, z, rMu, iMu, int M); } /* Need to call kernel one more time if M is not */ /* perfect multiple of CHUNK SIZE */ } Chunking k-space data to fit into constant memory

27 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 27 __global__ void cmpFHd(float* rPhi, iPhi, phiMag, x, y, z, rMu, iMu, int M) { int n = blockIdx.x * FHD_THREADS_PER_BLOCK + threadIdx.x; float xn_r = x[n]; float yn_r = y[n]; float zn_r = z[n]; float rFhDn_r = rFhD[n]; float iFhDn_r = iFhD[n]; for (m = 0; m < M; m++) { float expFhD = 2*PI*(kx[m]*xn_r+ky[m]*yn_r+kz[m]*zn_r); float cArg = cos(expFhD); float sArg = sin(expFhD); rFhDn_r += rMu[m]*cArg – iMu[m]*sArg; iFhDn_r += iMu[m]*cArg + rMu[m]*sArg; } rFhD[n] = rFhD_r; iFhD[n] = iFhD_r; } Revised Kernel for Constant Memory

28 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 28 25 (a) k-space data stored in separate arrays. (b) k-space data stored in an array whose elements are structs. Figure 7.14 Effect of k-space data layout on constant cache efficiency.

29 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 29 struct kdata { float x, float y, float z; } k; __constant__ struct kdata k_c[CHUNK_SIZE]; … __ void main() { int i; for (i = 0; i < M/CHUNK_SIZE; i++); cudaMemcpy(k_c,k,12*CHUNK_SIZE, cudaMemCpyHostToDevice); cmpFHD >> (); } 6 Figure 7.15 adjusting k-space data layout to improve cache efficiency

30 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 30 __global__ void cmpFHd(float* rPhi, iPhi, phiMag, x, y, z, rMu, iMu, int M) { int n = blockIdx.x * FHD_THREADS_PER_BLOCK + threadIdx.x; float xn_r = x[n]; float yn_r = y[n]; float zn_r = z[n]; float rFhDn_r = rFhD[n]; float iFhDn_r = iFhD[n]; for (m = 0; m < M; m++) { float expFhD = 2*PI*(k[m].x*xn_r+k[m].y*yn_r+k[m].z*zn_r); float cArg = cos(expFhD); float sArg = sin(expFhD); rFhDn_r += rMu[m]*cArg – iMu[m]*sArg; iFhDn_r += iMu[m]*cArg + rMu[m]*sArg; } rFhD[n] = rFhD_r; iFhD[n] = iFhD_r; } 6 Figure 7.16 Adjusting the k-space data memory layout in the F H d kernel

31 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 31 13 Q(float* x,y,z,rQ,iQ,kx,ky,kz,phi, int startM,endM) { n = blockIdx.x*TPB + threadIdx.x for (m = startM; m < endM; m++) { exQ = 2*PI*(kx[m]*x[n] + ky[m]*y[n] + kz[m]*z[n]) rQ[n] += phi[m] * cos(exQ) iQ[n] += phi[m] * sin(exQ) } From C to CUDA: Step 2 Where are the potential bottlenecks? Bottlenecks Memory BW Trig ops Overheads (branches, addr calcs)

32 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 32 Step 3: Overcoming bottlenecks 14 LS recon on CPU (SP) –Q: 45 hours, 0.5 GFLOPS –F H d: 7 hours, 0.7 GFLOPS Counting each trig op as 1 FLOP

33 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 33 Step 3: Overcoming Bottlenecks (Mem BW) 15 Register allocate pixel data –Inputs (x, y, z); Outputs (rQ, iQ) Exploit temporal and spatial locality in access to scan data –Constant memory + constant caches –Shared memory

34 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 34 Step 3: Overcoming Bottlenecks (Mem BW) Register allocation of pixel data –Inputs (x, y, z); Outputs (rQ, iQ) –FP arithmetic to off-chip loads: 2 to 1 Performance –5.1 GFLOPS (Q), 5.4 GFLOPS (F H d) Still bottlenecked on memory BW 16

35 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 35 Step 3: Overcoming Bottlenecks (Mem BW) Old bottleneck: off-chip BW –Solution: constant memory –FP arithmetic to off-chip loads: 284 to 1 Performance –18.6 GFLOPS (Q), 22.8 GFLOPS (F H d) New bottleneck: trig operations 17

36 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 36 Sidebar: Estimating Off-Chip Loads with Const Cache How can we approximate the number of off-chip loads when using the constant caches? Given: 128 tpb, 4 blocks per SM, 256 scan points per grid Assume no evictions due to cache conflicts 7 accesses to global memory per thread (x, y, z, rQ x 2, iQ x 2) –4 blocks/SM * 128 threads/block * 7 accesses/thread = 3,584 global mem accesses 4 accesses to constant memory per scan point (kx, ky, kz, phi) –256 scan points * 4 loads/point = 1,024 constant mem accesses Total off-chip memory accesses = 3,584 + 1,024 = 4,608 Total FP arithmetic ops = 4 blocks/SM * 128 threads/block * 256 iters/thread * 10 ops/iter = 1,310,720 FP arithmetic to off-chip loads: 284 to 1 18

37 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 37 Step 3: Overcoming Bottlenecks (Trig) Old bottleneck: trig operations –Solution: SFUs Performance –98.2 GFLOPS (Q), 92.2 GFLOPS (F H d) New bottleneck: overhead of branches and address calculations 19

38 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 38 Sidebar: Effects of Approximations Avoid temptation to measure only absolute error (I 0 – I) –Can be deceptively large or small Metrics –PSNR: Peak signal-to-noise ratio –SNR: Signal-to-noise ratio Avoid temptation to consider only the error in the computed value –Some apps are resistant to approximations; others are very sensitive 20 A.N. Netravali and B.G. Haskell, Digital Pictures: Representation, Compression, and Standards (2nd Ed), Plenum Press, New York, NY (1995).

39 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 39 Step 3: Overcoming Bottlenecks (Overheads) Old bottleneck: Overhead of branches and address calculations –Solution: Loop unrolling and experimental tuning Performance –179 GFLOPS (Q), 145 GFLOPS (F H d) 21

40 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 40 Experimental Tuning: Tradeoffs In the Q kernel, three parameters are natural candidates for experimental tuning –Loop unrolling factor (1, 2, 4, 8, 16) –Number of threads per block (32, 64, 128, 256, 512) –Number of scan points per grid (32, 64, 128, 256, 512, 1024, 2048) Can’t optimize these parameters independently –Resource sharing among threads (register file, shared memory) –Optimizations that increase a thread’s performance often increase the thread’s resource consumption, reducing the total number of threads that execute in parallel Optimization space is not linear –Threads are assigned to SMs in large thread blocks –Causes discontinuity and non-linearity in the optimization space 22

41 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 41 Experimental Tuning: Example Increase in per-thread performance, but fewer threads: Lower overall performance 23

42 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 42 Experimental Tuning: Scan Points Per Grid 24

43 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 43 Sidebar: Cache-Conscious Data Layout kx, ky, kz, and phi components of same scan point have spatial and temporal locality –Prefetching –Caching Old layout does not fully leverage that locality New layout does fully leverage that locality 25

44 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 44 Experimental Tuning: Scan Points Per Grid (Improved Data Layout) 26

45 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 45 Experimental Tuning: Loop Unrolling Factor 27

46 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 46 Sidebar: Optimizing the CPU Implementation Optimizing the CPU implementation of your application is very important –Often, the transformations that increase performance on CPU also increase performance on GPU (and vice-versa) –The research community won’t take your results seriously if your baseline is crippled Useful optimizations –Data tiling –SIMD vectorization (SSE) –Fast math libraries (AMD, Intel) –Classical optimizations (loop unrolling, etc) Intel compiler (icc, icpc) 28

47 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 47 Summary of Results QFHdFHd ReconstructionRun Time (m) GFLOPRun Time (m) GFLOPLinear Solver (m) Recon. Time (m) Gridding + FFT (CPU, DP) N/A 0.39 LS (CPU, DP)4009.00.3518.00.41.59519.59 LS (CPU, SP)2678.70.5342.30.71.61343.91 LS (GPU, Naïve)260.25.141.05.41.6542.65 LS (GPU, CMem) 72.018.69.822.81.5711.37 LS (GPU, CMem, SFU) 13.698.22.492.21.604.00 LS (GPU, CMem, SFU, Exp) 7.5178.91.5144.51.693.19 29 8X

48 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 48 Summary of Results 30 QFHdFHd ReconstructionRun Time (m)GFLOPRun Time (m) GFLOPLinear Solver (m) Recon. Time (m) Gridding + FFT (CPU, DP) N/A 0.39 LS (CPU, DP)4009.00.3518.00.41.59519.59 LS (CPU, SP)2678.70.5342.30.71.61343.91 LS (GPU, Naïve)260.25.141.05.41.6542.65 LS (GPU, CMem)72.018.69.822.81.5711.37 LS (GPU, CMem, SFU) 13.698.22.492.21.604.00 LS (GPU, CMem, SFU, Exp) 7.5178.91.5144.51.693.19 108X228X357X

49 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 49 Questions? 31 + = Scanner image released distributed under GNU Free Documentation License. GeForce 8800 GTX image obtained from http://www.nvnews.net/previews/geforce_8800_gtx/index.shtml

50 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 50 Algorithms to Accelerate for (K = 0; K < numK; K++) rRho[K] = rPhi[K]*rD[K] + iPhi[K]*iD[K] iRho[K] = rPhi[K]*iD[K] - iPhi[K]*rD[K] for (X = 0; X < numP; X++) for (K = 0; K < numK; K++) exp = 2*PI*(kx[K]*x[X] + ky[K]*y[X] + kz[K]*z[X]) cArg = cos(exp) sArg = sin(exp) rFH[X] += rRho[K]*cArg – iRho[K]*sArg iFH[X] += iRho[K]*cArg + rRho[K]*sArg Compute F H d Inner loop –14 FP MUL or ADD ops –4 FP trig ops –12 loads (naively)

51 © David Kirk/NVIDIA and Wen-mei W. Hwu, 2007-2010 ECE408, University of Illinois, Urbana-Champaign 51 Experimental Methodology Reconstruct a 3D image of a human brain 1 –3.2 M scan data points acquired via 3D spiral scan –256K pixels Compare performance several reconstructions –Gridding + FFT recon 1 on CPU (Intel Core 2 Extreme Quadro) –LS recon on CPU (double-precision, single-precision) –LS recon on GPU (NVIDIA GeForce 8800 GTX) Metrics –Reconstruction time: compute F H d and run linear solver –Run time: compute Q or F H d 1 Courtesy of Keith Thulborn and Ian Atkinson, Center for MR Research, University of Illinois at Chicago 8

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