Presentation is loading. Please wait.

Presentation is loading. Please wait.

Lecture 13: Logic Emulation October 25, 2004 ECE 697F Reconfigurable Computing Lecture 13 Logic Emulation.

Published byNigel Julius Barrett Modified over 8 years ago

Similar presentations

Presentation on theme: "Lecture 13: Logic Emulation October 25, 2004 ECE 697F Reconfigurable Computing Lecture 13 Logic Emulation."— Presentation transcript:

1 Lecture 13: Logic Emulation October 25, 2004 ECE 697F Reconfigurable Computing Lecture 13 Logic Emulation

2 Lecture 13: Logic Emulation October 25, 2004 Overview Background Rent’s Rule Overcoming pin limitations through scheduling “Virtual wires” implementation Results / Future work

3 Lecture 13: Logic Emulation October 25, 2004 The Challenge Making a large multi-FPGA system is easy. Making it programmable is hard. New approach is a software technology that facilitates hardware implementation. Effectively make a large number of discrete devices look like one large one. Leads to low-cost, scalable multi-FPGA substrate.

4 Lecture 13: Logic Emulation October 25, 2004 Logic Emulation Emulation takes a sizable amount of resources Compilation time can be large due to FPGA compiles One application: also direct ties to other FPGA computing applications.

5 Lecture 13: Logic Emulation October 25, 2004 Are Meshes Realistic? The number of wires leaving a partition grows with Rent’s Rule P = KG B Perimeter grows as G 0.5 but unfortunately most circuits grow at G B where B > 0.5 Effectively devices highly pin limited What does this mean for meshes?

6 Lecture 13: Logic Emulation October 25, 2004 Possible Device Scenarios Rent’s Rule indicates that pin limited situation is getting worse. Frequently some logic must be left unused leading to limited utilization Perhaps this logic can be “reclaimed”

7 Lecture 13: Logic Emulation October 25, 2004 Partition vs FPGA Pin Count FPGAs don’t have enough pins Problem may or may not get worse depending on “structured” design.

8 Lecture 13: Logic Emulation October 25, 2004 Virtual Wires Overcome pin limitations by multiplexing pins and signals Schedule when communication will take place.

9 Lecture 13: Logic Emulation October 25, 2004 Virtual Wires Software Flow Global router enhanced to include scheduling and embedding. Multiplexing logic synthesized from FPGA logic.

10 Lecture 13: Logic Emulation October 25, 2004 A Simple Example FPGA 1FPGA 2 FPGA 3FPGA 4

11 Lecture 13: Logic Emulation October 25, 2004 Clocking Strategy Evaluation and communication split into phases Longest dependency path determines number of phases -Overall emulation performance

12 Lecture 13: Logic Emulation October 25, 2004 Example Scheduling Initial phase requires one uClk for computation, one for communication. Second phase requires 2 communication uClks due to through hop. Note this example assumed needed bandwidth was available.

13 Lecture 13: Logic Emulation October 25, 2004 Routing Algorithm For each phase, only some internal signals are ready for routing. Routing resources between FPGAs may be considered channels. Solution: Route signals use maze route for each phase. If available bandwidth not present, delay signals until later phases.

14 Lecture 13: Logic Emulation October 25, 2004 Worst Case Microcycle Count Most designs dominated by latency bound. If original design has been pipelined this is less of an issue V >= max ( L*D, P C /P f ) L = critical path length D = network diameter P C = max circuit partition pin count P f = FPGA pin count

15 Lecture 13: Logic Emulation October 25, 2004 Improved Scheduling Overlap computation and communication. Effectively create a “data flow” of information Schedule communication to happen as soon as possible -No need for phases. uCLK

16 Lecture 13: Logic Emulation October 25, 2004 Physical Implementation Small finite state machine encoded and placed in each FPGA Current implementation is one-hot encoding.

17 Lecture 13: Logic Emulation October 25, 2004 System Implementation Low cost hardware So simple a graduate student can build it

18 Lecture 13: Logic Emulation October 25, 2004 Benchmark Designs Sparcle – modified Sparc processor -17K gates -4,352 bits of memory -Emulated in circuit. CMMU – cache controller for scalable multiprocessor system -85K gates -Designed as gate array and optimized with SIS Palindrome -14K gates -systolic

19 Lecture 13: Logic Emulation October 25, 2004 Emulation Results At least 31 FPGAs needed for HW full connectivity (>100 for torus) Some degradation in overall system performance.

20 Lecture 13: Logic Emulation October 25, 2004 Device Utilization Approximately 45% of CLBs used for design logic. ~10% virtual wires overhead

21 Lecture 13: Logic Emulation October 25, 2004 Utilizations As devices scale projected utilization increases Hardwired approach doesn’t scale Equation ->

22 Lecture 13: Logic Emulation October 25, 2004 Future Directions Incremental compilation -FPGAs take a long time to compile -Desirable to isolate changes to a small number of partitions -Scheduling simplifies issue by allowing additional communication cycles – Rest of circuit unchanged! Perhaps isolate at the macroblock stage Impact on topology.

23 Lecture 13: Logic Emulation October 25, 2004 Virtualized Memory Multiplex a single-ported memory over time to create a multi-port memory Allows use of low-cost memories in system development Also multiplexed logic analyzer interface. A0A0 A1A1 A D D0D0 D1D1 D0D0 D1D1

24 Lecture 13: Logic Emulation October 25, 2004 Summary Virtual wires overcome pin limitations by intelligently multiplexing I/O signals Key CAD step is scheduling. Simplifies routing and partitioning. Latest push is towards incremental compilation Commercialized by Ikos Systems (now Mentor Graphics)

Download ppt "Lecture 13: Logic Emulation October 25, 2004 ECE 697F Reconfigurable Computing Lecture 13 Logic Emulation."

Similar presentations

RAMP Gold : An FPGA-based Architecture Simulator for Multiprocessors Zhangxi Tan, Andrew Waterman, David Patterson, Krste Asanovic Parallel Computing Lab,

RAMP Gold : An FPGA-based Architecture Simulator for Multiprocessors Zhangxi Tan, Andrew Waterman, David Patterson, Krste Asanovic Parallel Computing Lab,
ECE-777 System Level Design and Automation Hardware/Software Co-design

ECE-777 System Level Design and Automation Hardware/Software Co-design
Implementation Approaches with FPGAs Compile-time reconfiguration (CTR) CTR is a static implementation strategy where each application consists of one.

Implementation Approaches with FPGAs Compile-time reconfiguration (CTR) CTR is a static implementation strategy where each application consists of one.
THE RAW MICROPROCESSOR: A COMPUTATIONAL FABRIC FOR SOFTWARE CIRCUITS AND GENERAL- PURPOSE PROGRAMS Taylor, M.B.; Kim, J.; Miller, J.; Wentzlaff, D.; Ghodrat,

THE RAW MICROPROCESSOR: A COMPUTATIONAL FABRIC FOR SOFTWARE CIRCUITS AND GENERAL- PURPOSE PROGRAMS Taylor, M.B.; Kim, J.; Miller, J.; Wentzlaff, D.; Ghodrat,
Lecture 9: Coarse Grained FPGA Architecture October 6, 2004 ECE 697F Reconfigurable Computing Lecture 9 Coarse Grained FPGA Architecture.

Lecture 9: Coarse Grained FPGA Architecture October 6, 2004 ECE 697F Reconfigurable Computing Lecture 9 Coarse Grained FPGA Architecture.
Graduate Computer Architecture I Lecture 16: FPGA Design.

Graduate Computer Architecture I Lecture 16: FPGA Design.
Minimizing Clock Skew in FPGAs

Minimizing Clock Skew in FPGAs
Balancing Interconnect and Computation in a Reconfigurable Array Dr. André DeHon BRASS Project University of California at Berkeley Why you don’t really.

Balancing Interconnect and Computation in a Reconfigurable Array Dr. André DeHon BRASS Project University of California at Berkeley Why you don’t really.
Seven Minute Madness: Special-Purpose Parallel Architectures Dr. Jason D. Bakos.

Seven Minute Madness: Special-Purpose Parallel Architectures Dr. Jason D. Bakos.
ECE669 L12: Interconnection Network Performance March 9, 2004 ECE 669 Parallel Computer Architecture Lecture 12 Interconnection Network Performance.

ECE669 L12: Interconnection Network Performance March 9, 2004 ECE 669 Parallel Computer Architecture Lecture 12 Interconnection Network Performance.
Lecture 2: Field Programmable Gate Arrays I September 5, 2013 ECE 636 Reconfigurable Computing Lecture 2 Field Programmable Gate Arrays I.

Lecture 2: Field Programmable Gate Arrays I September 5, 2013 ECE 636 Reconfigurable Computing Lecture 2 Field Programmable Gate Arrays I.
ECE669 L11: Static Routing Architectures March 4, 2004 ECE 669 Parallel Computer Architecture Lecture 11 Static Routing Architectures.

ECE669 L11: Static Routing Architectures March 4, 2004 ECE 669 Parallel Computer Architecture Lecture 11 Static Routing Architectures.
ENGIN112 L38: Programmable Logic December 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic.

ENGIN112 L38: Programmable Logic December 5, 2003 ENGIN 112 Intro to Electrical and Computer Engineering Lecture 38 Programmable Logic.
CS294-6 Reconfigurable Computing Day 8 September 17, 1998 Interconnect Requirements.

CS294-6 Reconfigurable Computing Day 8 September 17, 1998 Interconnect Requirements.
FPGA Based Video Codec: Implementation and Techniques An 18-796 Seminar Series Markus Adhiwiyogo Benjamin Ernest-Jones Matt Richey.

FPGA Based Video Codec: Implementation and Techniques An Seminar Series Markus Adhiwiyogo Benjamin Ernest-Jones Matt Richey.
Programmable logic and FPGA

Programmable logic and FPGA
Modern trends in computer architecture and semiconductor scaling are leading towards the design of chips with more and more processor cores. Highly concurrent.

Modern trends in computer architecture and semiconductor scaling are leading towards the design of chips with more and more processor cores. Highly concurrent.
Dynamic NoC. 2 Limitations of Fixed NoC Communication NoC for reconfigurable devices:  NOC: a viable infrastructure for communication among task dynamically.

Dynamic NoC. 2 Limitations of Fixed NoC Communication NoC for reconfigurable devices:  NOC: a viable infrastructure for communication among task dynamically.
Lecture 9: Multi-FPGA System Software October 3, 2013 ECE 636 Reconfigurable Computing Lecture 9 Multi-FPGA System Software.

Lecture 9: Multi-FPGA System Software October 3, 2013 ECE 636 Reconfigurable Computing Lecture 9 Multi-FPGA System Software.
The Memory/Logic Interface in FPGA’s with Large Embedded Memory Arrays The Memory/Logic Interface in FPGA’s with Large Embedded Memory Arrays Steven J.

The Memory/Logic Interface in FPGA’s with Large Embedded Memory Arrays The Memory/Logic Interface in FPGA’s with Large Embedded Memory Arrays Steven J.

Similar presentations

Ads by Google