1. Virtual Memory Part 1 Li-Shiuan Peh Computer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology May 2, 2012L22-1 http://csg.csail.mit.edu/6.S078

2. Virtual Memory Basics physical address virtual address machine language address Address Mapping ISA Physical Memory (Caches, DRAM) May 2, 2012 L22-2http://csg.csail.mit.edu/6.S078 lw $t0, 32 ($s3) 0xABCDEFGH 01HGFEDCB 32-bit ISA1GB DRAM (2 30 ) lw $t0, 32 ($s3) 0xABCDEFGHIJKLMNOP 0xHGFEDCBA 32-bit ISA4GB DRAM (2 32 ) lw $t0, 32 ($s3) 0xABCDEFGHIJKLMNOP 0xIHGFEDCBA 64-bit ISA64GB DRAM (2 36 )

3. Virtual Memory Basics: Pages physical address virtual address machine language address Address Mapping ISA Physical Memory May 2, 2012 L22-3http://csg.csail.mit.edu/6.S078 lw $t0, 32 ($s3) 0xABCDEFGH 0xHGFEDFGH physical address virtual address machine language address Address Mapping (Page Tables) ISA Physical Memory Mapping individual addresses incurs too much overhead: Let’s page it: Chunk address space! lw $t0, 32 ($s3) Page Index:0xABCDE 0xHGFED Page Offset:0xFGH 0xFGH

4. Processor generated address can be interpreted as a pair A page table contains the physical address of the base of each page Paged Memory Systems Page tables make it possible to access and store pages of a program non-contiguously 0 1 2 3 Address Space of User-1 Page Table of User-1 0 1 2 3 1 0 2 3 page number offset May 2, 2012 L22-4http://csg.csail.mit.edu/6.S078

5. Why Virtual Memory? Illusion of a large, private, uniform store Protection & Privacy several users, each with their private address space and one or more shared address spaces page table name space Demand Paging Provides the ability to run programs larger than the primary memory Hides differences in machine configurations The price is address translation on each memory reference OS user i Primary Memory Swapping Store VAPA mapping PageTbl May 2, 2012 L22-5http://csg.csail.mit.edu/6.S078

6. Why Virtual Memory: Reason #1: Protection & Privacy So: Private Address Space per User Each user has a page table Page table contains an entry for each user page VA1 User 1 Page Table VA1 User 2 Page Table VA1 User 3 Page Table Physical Memory free OS pages May 2, 2012 L22-6http://csg.csail.mit.edu/6.S078

7. Address Translation & Protection Physical Address Virtual Address Address Translation Virtual Page No. (VPN)offset Physical Page No. (PPN)offset Protection Check Exception? Kernel/User Mode Read/Write Every instruction access and data access needs address translation and protection checks May 2, 2012 L22-7http://csg.csail.mit.edu/6.S078

8. Why Virtual Memory: Reason #2: Demand Paging (VM >> PM) So: Page Table keeps track of disk vs. DRAM CPU 0: 1: N-1: Physical Memory (DRAM) Load 0xf0 0: 1: P-1: Page Table Store 0x10 Disk Virtual Addresses Physical Addresses Page Faults: Page not in DRAM, so, load from Disk to DRAM!

9. Linear Page Table: Implementing Demand Paging and Protection VPN Offset Virtual address PT Base Register VPN Data word Data Pages Offset PPN DPN PPN Page Table DPN PPN DPN PPN Page Table Entry (PTE) contains: A bit to indicate if a page exists PPN (physical page number) for a memory- resident page DPN (disk page number) for a page on the disk Status bits for protection and usage OS sets the Page Table Base Register whenever active user process changes May 2, 2012 L22-9http://csg.csail.mit.edu/6.S078

10. Page Tables in Physical Memory: 1 memory access for translation + 1 memory access for actual access! +? VA1 User 1 PT User 1 PT User 2 VA1 User 2 Idea: cache the address translation of frequently used pages – Translation Look- aside Buffer (TLB) May 2, 2012 L22-10http://csg.csail.mit.edu/6.S078 translation access

11. A cache for address translations: Translation Lookaside Buffers (TLB) Cache address translations in TLB TLB hitSingle Cycle Translation TLB miss Page Table Walk to find Page Table Entry in DRAM, and refill into TLB VPN offset V R W D tag PPN physical address PPN offset virtual address hit? May 2, 2012 L22-11http://csg.csail.mit.edu/6.S078

12. Virtual Memory: Translation + Access physical address virtual address machine language address Address Mapping ISA Physical Memory (Caches, DRAM) May 2, 2012 L22-12http://csg.csail.mit.edu/6.S078 Physical Memory handles the access from DRAM Virtual Memory handles the translation and filling DRAM from Disk

13. Virtual Memory: putting it all together Virtual Address TLB Lookup Page Table Walk (DRAM) Update TLB Page Fault (OS loads page) Protection Check Physical Address (to cache hierarchy) miss hit the page is  memory  memory denied permitted Protection Fault hardware hardware or software software SEGFAULT Where? May 2, 2012 L22-13http://csg.csail.mit.edu/6.S078 Translation miss! Access miss!

14. Handling a TLB Miss Software (MIPS, Alpha) TLB miss causes an exception and the operating system walks the page tables and reloads TLB. A privileged “untranslated” addressing mode used for walk Hardware (SPARC v8, x86, PowerPC) A memory management unit (MMU) walks the page tables and reloads the TLB May 2, 2012 L22-14http://csg.csail.mit.edu/6.S078

15. Page Fault Handler When the referenced page is not in DRAM: The missing page is located (or created) It is brought in from disk, and page table is updated Another job may be run on the CPU while the first job waits for the requested page to be read from disk If no free pages are left, a page is swapped out approximate LRU replacement policy Since it takes a long time (msecs) to transfer a page, page faults are handled completely in software (OS) Untranslated addressing mode is essential to allow kernel to access page tables May 2, 2012 L22-15http://csg.csail.mit.edu/6.S078

16. Virtual memory + processor + caches May 2, 2012 L22-16http://csg.csail.mit.edu/6.S078 PC Inst TLB Inst. Cache D Decode EM Data TLB Data Cache W + TLB miss? Page Fault? Protection violation? TLB miss? Page Fault? Protection violation?

17. Physical or Virtual Address Caches? one-step process in case of a hit (+) cache needs to be flushed on a context switch unless address space identifiers (ASIDs) included in tags (-) aliasing problems due to the sharing of pages (-) CPU Physical Cache TLB Primary Memory VA PA Alternative: place the cache before the TLB CPU VA (StrongARM) Virtual Cache PA TLB Primary Memory May 2, 2012 L22-17http://csg.csail.mit.edu/6.S078

18. Aliasing in Virtual-Address Caches VA 1 VA 2 Page Table Data Pages PA VA 1 VA 2 1st Copy of Data at PA 2nd Copy of Data at PA TagData Two virtual pages share one physical page Virtual cache can have two copies of same physical data. Writes to one copy not visible to reads of other! General Solution: Disallow aliases to coexist in cache Software (i.e., OS) solution for direct-mapped cache VAs of shared pages must agree in cache index bits Hardware solution for direct-mapped cache Cache size < Page size May 2, 2012 L22-18http://csg.csail.mit.edu/6.S078

19. Let’s build! May 2, 2012 L22-19http://csg.csail.mit.edu/6.S078 F Fetch D Decode R Reg Read X Execute M Memory W Write- back Virtual I$ VA TLB I$ miss (VA) Virtual D$ VA D$ miss (VA) Physical L2$ PA Page Table Walker TLB miss DRAM (Page Table) Page Fault Exception DRAM (Pages) Page Fault