1. Fundamentals of Programming Languages-II Subject Code: 110010 Teaching SchemeExamination Scheme Theory: 1 Hr./WeekOnline Examination: 50 Marks Practical: 2 Hrs./Week

2. Unit-I Microprocessors and Micro-Controllers Architectures and Programming Concepts 2

3. 1.5 SEGMENTATION AND PAGING 3

4. Basic Concepts: Pure Paging and Segmentation Paging: memory divided into equal-sized frames. All process pages loaded into non- necessarily contiguous frames Segmentation: each process divided into variable-sized segments. All process segments loaded into dynamic partitions that are not necessarily contiguous 4

5. Hardware Translation Translation from logical to physical can be done in software but without protection – Why “without” protection? Hardware support is needed to ensure protection Simplest solution with two registers: base and size Processor Physical memory translation box (MMU)

6. Segmentation Hardware virtual address offset segment segment table + physical address

7. Segmentation Segments are of variable size Translation done through a set of (base, size, state) registers - segment table State: valid/invalid, access permission, reference bit, modified bit Segments may be visible to the programmer and can be used as a convenience for organizing the programs and data (i.e code segment or data segments) 7

8. Paging hardware virtual address page table + physical address page # offset

9. Paging Pages are of fixed size The physical memory corresponding to a page is called page frame Translation done through a page table indexed by page number Each entry in a page table contains the physical frame number that the virtual page is mapped to and the state of the page in memory State: valid/invalid, access permission, reference bit, modified bit, caching Paging is transparent to the programmer 9

10. Combined Paging and Segmentation Some MMU combine paging with segmentation Segmentation translation is performed first The segment entry points to a page table for that segment The page number portion of the virtual address is used to index the page table and look up the corresponding page frame number Segmentation not used much anymore so we’ll concentrate on paging – UNIX has simple form of segmentation but does not require any hardware support 10

11. Address Translation CPU pd p f fd f d page table Memory virtual address physical address 11

12. Translation Lookaside Buffers Translation on every memory access  must be fast What to do? Caching, of course … Why does caching work? That is, we still have to lookup the page table entry and use it to do translation, right? Same as normal memory cache – cache is smaller so can spend more $$ to make it faster 12

13. Translation Lookaside Buffer Cache for page table entries is called the Translation Lookaside Buffer (TLB) – Typically fully associative – No more than 64 entries Each TLB entry contains a page number and the corresponding PT entry On each memory access, we look for the page  frame mapping in the TLB 13

14. Translation Lookaside Buffer 14

15. Address Translation CPU pd fd f d TLB Memory virtual address physical address p/f f 15

16. TLB Miss What if the TLB does not contain the appropriate PT entry? – TLB miss – Evict an existing entry if does not have any free ones Replacement policy? – Bring in the missing entry from the PT TLB misses can be handled in hardware or software – Software allows application to assist in replacement decisions 16

17. Where to Store Address Space? Address space may be larger than physical memory Where do we keep it? Where do we keep the page table? 17

18. Where to Store Address Space? On the next device down our storage hierarchy, of course … Memory VM Disk

19. Where to Store Page Table? Interestingly, use memory to “enlarge” view of memory, leaving LESS physical memory This kind of overhead is common – For example, OS uses CPU cycles to implement abstraction of threads Gotta know what the right trade- off is Have to understand common application characteristics Have to be common enough! Page tables can get large. What to do? OS Code Globals Stack Heap P1 Page Table P0 Page Table In memory, of course …

20. Two-Level Page-Table Scheme 20

21. Two-Level Paging Example A logical address (on 32-bit machine with 4K page size) is divided into: – a page number consisting of 20 bits. – a page offset consisting of 12 bits. Since the page table is paged, the page number is further divided into: – a 10-bit page number. – a 10-bit page offset. 21

22. Two-Level Paging Example Thus, a logical address is as follows: where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table. page number page offset pipi p2p2 d 10 12 22

23. Address-Translation Scheme Address-translation scheme for a two-level 32-bit paging architecture 23

24. Multilevel Paging and Performance Since each level is stored as a separate table in memory, covering a logical address to a physical one may take four memory accesses. Even though time needed for one memory access is quintupled, caching permits performance to remain reasonable. Cache hit rate of 98 percent yields: effective access time = 0.98 x 120 + 0.02 x 520 = 128 nanoseconds. which is only a 28 percent slowdown in memory access time. 24

25. Paging the Page Table Page tables can still get large What to do? P1 PT P0 PT Kernel PT Non-page-able Page-able OS Segment Page the page table!

26. Inverted Page Table One entry for each real page of memory. Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page. Decreases memory needed to store each page table, but increases time needed to search the table when a page reference occurs. Use hash table to limit the search to one — or at most a few — page-table entries. 26

27. Inverted Page Table Architecture 27

28. How to Deal with VM  Size of Physical Memory? If address space of each process is  size of physical memory, then no problem – Still useful to deal with fragmentation When VM larger than physical memory – Part stored in memory – Part stored on disk How do we make this work? 28

29. Demand Paging To start a process (program), just load the code page where the process will start executing As process references memory (instruction or data) outside of loaded page, bring in as necessary How to represent fact that a page of VM is not yet in memory? 0 1 2 1v i i A B C 0 1 2 3 A 0 1 2 B C VM Paging TableMemory Disk 29

30. Vs. Swapping 30

31. Page Fault What happens when process references a page marked as invalid in the page table? – Page fault trap – Check that reference is valid – Find a free memory frame – Read desired page from disk – Change valid bit of page to v – Restart instruction that was interrupted by the trap Is it easy to restart an instruction? What happens if there is no free frame? 31

32. Page Fault (Cont’d) So, what can happen on a memory access? – TLB miss  read page table entry – TLB miss  read kernel page table entry – Page fault for necessary page of process page table – All frames are used  need to evict a page  modify a process page table entry TLB miss  read kernel page table entry – Page fault for necessary page of process page table – Uh oh, how deep can this go? – Read in needed page, modify page table entry, fill TLB 32

33. Cost of Handling a Page Fault Trap, check page table, find free memory frame (or find victim) … about 200 - 600  s Disk seek and read … about 10 ms Memory access … about 100 ns Page fault degrades performance by ~100000!!!!! – And this doesn’t even count all the additional things that can happen along the way Better not have too many page faults! If want no more than 10% degradation, can only have 1 page fault for every 1,000,000 memory accesses OS had better do a great job of managing the movement of data between secondary storage and main memory 33

34. 1.6 PROCESSING OF INTERRUPTS AND EXCEPTIONS 34

35. INTERRUPTS The event that causes the interruption is called interrupt and the special routine which is executed is called interrupt service routine. When many I/O devices are connected to a microprocessor based system, one or more than one of the I/O devices may request for service at any time. The microprocessor stops the execution of the current program and gives service to the I/O devices. This feature is called as interrupt. 35

36. The interrupts are classified as: 1.Single level interrupts 2.Multi level interrupts In a single level interrupt there can be many interrupting devices. But all interrupt requests are made via a single input pin of the CPU. In multilevel interrupts, processor has more than one interrupt pins. 1.The processor completes its current instruction. No instruction is cut off in the middle of its execution. 36

37. 2.The program counter’s current contents are stored on the stack. During the execution of the program counter is pointing to the memory location for the next instruction. 3.The program counter is loaded with the address of an interrupt service routine. 4.Program execution continues with the instruction taken from the memory location pointed by the new program counter contents. 5.The interrupt program continues to execute until a return instruction is executed. 37

38. 6.After execution of the RET instruction processor gets the old address of the program counter from the stack and puts it back into the program counter. This allows the interrupted program to continue executing at the instruction following one where it was interrupted. 38

39. Exceptions The internally generated errors which produce an interrupt for microprocessor are called exceptions. The exceptions are classified as  Faults: Faults are the exceptions that are detected and serviced before the execution of the faulting instruction.  Traps: Traps are exceptions that are reported immediately after the execution of the instructions which causes the problem.  Aborts: Aborts are exceptions which do not permit the precise location of the instruction causing the exception to be determined. Aborts are used to report severe errors, such as hardware error, or illegal values in the system tables. 39

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