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11/5/2015Mircea Bogdan1 Annie’s Central Card Status Report - 8/21/2015 The University of Chicago.

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Presentation on theme: "11/5/2015Mircea Bogdan1 Annie’s Central Card Status Report - 8/21/2015 The University of Chicago."— Presentation transcript:

1 11/5/2015Mircea Bogdan1 Annie’s Central Card Status Report - 8/21/2015 The University of Chicago

2 6U VME32 or VME 64x Format Can work as Stand Alone ACC Specs General 11/5/2015Mircea Bogdan2 QSFP 8 x RJ45 RJ45 Ethernet SMA USB LED VME P1 +5V VME P2 5 x SMA 16 x RJ45 or

3 ACC Specs System 11/5/2015Mircea Bogdan LVDS System Interface RJ45 with: -LVDS Clock in -2 x LVDS In -1 x LVDS Out 3 QSFP 8 x RJ45 RJ45 Ethernet SMA USB LED VME P1 +5V VME P2 5 x SMA 16 x RJ45 or

4 Annie System Interface and Clock Distribution 11/5/2015 Mircea Bogdan 4 System Clock IN RJ45 To FPGA 1:12 Note: Clocks to FE do not come from the FPGA; Clocks to FE are fixed, not from PLL. Clocks to FE are routed to equal length (+/-2.5mm) Local Clock To FE 8 x clocks LVDS IN LVDS OUT

5 ACC Specs Front End 11/5/2015Mircea Bogdan5 QSFP 8 x RJ45 RJ45 Ethernet SMA USB LED VME P1 +5V VME P2 5 x SMA 16 x RJ45 or LVDS Front End Interface Each FE Unit serviced via 2xRJ45 ACC can service 4 or 8 FE Units.

6 ACC Specs Front End Interface 11/5/2015 Mircea Bogdan 6 LVDS Out FE LVDS Out Clock Out LVDS In LVDS Out LVDS In/Out lines within one FE group are length matched to +/-5mm. (Clock Out line not included here)

7 11/5/2015Mircea Bogdan7 Annie Crate Master (ACM) Same module – Different Firmware ACC-0 ACC-3 ACC-7 … … Annie Crate Architecture Double Width ACM: One ACM Card can service 8 ACCs. System can be extended in multiples of 8, in a pyramid scheme. Single Width ACM: One ACM Card can service 4 ACCs. System can be extended in multiples of 4, in a pyramid scheme. New ACM can be designed to service up to 16 ACCs.

8 11/5/2015Mircea Bogdan ACC - situation and plans Questions/To Do List: -Finalize Specifications; -Finalize Schematic, Layout; http://edg.uchicago.edu/~bogdan/AnniesCentralCard/index.html -Finalize Top Level FPGA Design; -Start work on functional FPGA Design. 8


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