1. Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory16 January 2002 CMS Tracker FED Back End FPGA Frame_Sync_out0 Frame_Sync_In0 Readout_Sync_out0 Readout_Sync_In0 Monitor_out0 Monitor_In0 Data_stream0 Clock40 Reset FE0 Frame_Sync_out7 Frame_Sync_In7 Readout_Sync_out7 Readout_Sync_In7 Monitor_Sync_out7 Monitor_Sync_In7 Data_stream7 FE7 SLINK64 TTS VME Internal ADDR/CNTRL DATA IN DATA OUT QDR SSRAM TTCrx Configuration BSCAN SLINK Temp Sense Bank Voltages Core Voltage Bank DCI Resistors 16 x2 ~80 Config_In0 Config_out0 Full flags3 Temp Flags2 LM82 18 64 8 Clock40

2. Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory16 January 2002 CMS Tracker FED Back End FPGA FIFO Circular Buffers Frame_Syncs Readout_Syncs Monitor_Syncs x8 TTC Rx TTS 9 ‘VME’ DECODE CONTROL & MONITOR Data_stream0 Data_stream7 6418 Data In 20 Address 18 Data Out 64 SLINK 64 R/W Address Generator APV hdrs Lengths Bx,Ex Em Hdr diagnostics Data 80 Mhz 100 Khz 8 8 80 MHz 40 Mhz Clock40 Reset DCM x1 x2 x4 QDR SSRAM x4 burst BSCAN 320 MHz 80 MHz Lengths Header FF/PF Flags 2 8 1 1 1 Control

3. Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory16 January 2002 CMS Tracker FED - Back End FPGA Floorplan FE_FPGA_Inputs SLINK QDR XC2V1500FG676 - 396 I/O XC2V1000FG456 - 324 I/O XC2V2000FG676 - 456 I/O XC2V3000FG676 - 484 I/O Same frame 456 & 676 ? Clocks DiePackage VME

4. Electronic System Design GroupInstrumentation DepartmentRob Halsall et al.Rutherford Appleton Laboratory16 January 2002 CMS Tracker FED Back End FPGA Read Ptr Write Ptr 0 Write Ptr 1 Write Ptr 2 Write Ptr 7 Read Ptr Write Ptr 0 Write Ptr 1 Write Ptr 2 Write Ptr 7 Event N-1 Event N+1 Event N-1 Read Ptr Write Ptr 0 Write Ptr 1 Write Ptr 2 Write Ptr 7 Event N-1 Event N+1 #00000 #FFFFF Event N FE 0 FE 1 FE 7 T0T1T2 Header Ptr