1. Vertex Detector for GLD 3 Mar. 2005 Y. Sugimoto KEK

2. Vertex Detector Options Many options are proposed for ILC R.O. during train  20 frames/train  High speed readout R.O. between trains  20 registers/pixel or 20 times more pixels  High density design CCD Column Parallel CCD (CPCCD) In-situ Storage Image Sensor (ISIS) Fine Pixel CCD (FPCCD) CMOS Monolithic Active Pixel Sensor (MAPS) Flexible Active Pixel Sensor (FAPS) Others DEPFET

3. Vertex Detector Options FAPS Analog registers on each pixel Switch registers every 50  s Read out between trains

4. Vertex Detector Options ISIS CCD on each pixel Transfer in every 50  s Read out between trains

5. Vertex Detector Options FPCCD Accumulate hit signals for one train and read out between trains Keep low pixel occupancy by increasing number of pixels by x20 with respect to “standard” pixel detector As a result, pixel size should be as small as ~5x5  m 2 Epitaxial layer has to be fully depleted to minimize charge spread by diffusion Operation at low temperature to keep dark current negligible (r.o. cycle=200ms)

6. Challenges of FPCCD Pixel size Tracking efficiency Thin wafer and support structure Lorentz angle Low B is preferable Readout electronics Signal level is small (~500 e) Radiation hardness Relaxed by low temp. operation

7. Challenges of FPCCD Pixel size 5  m pixel has full-well capacity ~few k electrons CCD process 5  m pixel with poly-Si gate is easy Large size and fast readout require Al layer 5  m pixel with poly-Si gate and metal layer is not easy

8. Challenges of FPCCD Tracking efficiency In FPCCD, pixel occupancy would be low (<1%) but hit density mainly due to the pair-background is as high as ~40/mm 2 (B=3T, R=20mm) So, whether we can get good tracking efficiency or not is not trivial Extrapolation of tracks from Si intermediate tracker (SIT) with bunch ID capability will be necessary The study of tracking efficiency under high background rate is the most important and urgent issue Simulation framework to overlap background hits with physics events has to be constructed

9. Challenges of FPCCD Tracking efficiency Large number of background hits may cause tracking inefficiency: mis-identification of signal hit with background hit  : Background hit density  0 : Multiple scattering angle For a normal incident track; Angular and momentum dependence;

10. Challenges of FPCCD Tracking efficiency cos  p mis d=10mm,  =40/mm 2 d=2mm,  =40/mm 2 d=10mm,  =2/mm 2 Mis-identification Probability (p=1 GeV/c,t Si =50  m)

11. Challenges of FPCCD Tracking efficiency Some ideas for b.g. rejection (1): Hit cluster shape High Pt Signal Low Pt b.g. Z  (tracking capability with single layer!)

12. Challenges of FPCCD Some ideas for b.g. rejection (2): CCD doublet in proximity to reduce effect of M.S.

13. Challenges of FPCCD Lorentz angle tan  =  n B  n : electron mobility Carrier velocity saturates at high E field:  n =0.07 m 2 /Vs @T=300K, E=1x10 4 V/cm  n =0.045 m 2 /Vs @T=300K, E=2x10 4 V/cm Small angle can be cancelled by tilting the wafer B=3TB=5T E=1x10 4 V/cm  =12deg  =19deg E=2x10 4 V/cm  =7.7deg  =13deg

14. Advantages of FPCCD Free from beam-induced RF noise  x ~1.4  m even with digital readout Simple structure : advantageous for large size Active circuit only on the edge : easy to control temperature Readout speed: 15MHz is enough (CPCCD:>50MHz) CCD MAPS/FAPS/ISIS

15. Study Issues of FPCCD Short term goal (by the “Detector outline document”) Simulation study Tracking efficiency Physics implication (Flavor tagging) Hardware study (depends on funding) Charge spread in fully depleted CCDs Lorentz angle in B field  Optimization of wafer tilt angle Radiation hardness (difference in fully depleted CCD?) Show that FPCCD works as a vertex detector “in principle” Mid term goal (by “CDR”) Fabrication of prototype ladders Test the prototypes and demonstrate the performance Long term goal (by “LOI”) Engineering design of FPCCD Vertex Detector

16. Schedule 20052006 123456789101112123456789101112 LCWS05SnowmassVertex05Detector Outline Document ACFA8 Simulation w/o b.g B.G. overlap f.w. Tracking Eff. sim. Flavor Tag. Sim. LCWS06 Charge spread in CCDLorentz angle study Radiation hardness Design of prototype