1. Zheng Wu

2. Background Motivation Analysis Framework Intra-Core Cache Analysis Cache Conflict Analysis Optimization Techniques WCRT Analysis Experiment Setup Experiment Results Contribution Conclusion

3. Hard Real-time Systems –Worst case execution time: essential input for schedulability analysis Static Program Analysis –Program path modeling: infeasible path/ loop bound detection –Micro-architecture modeling: instruction/data cache, branch prediction, out-of-order pipeline. Distribution Actual WCET Execution Time Actual Observed Observed WCET

4. Concurrent Programs –Task interaction: control/data dependency, preemption. –Resource contention: Shared cache multi-core architectures Problem: shared L2 instruction cache contention. Core 1Core n CPU L1 Cache CPU L1 Cache L2 Cache ……

5. Message Sequence Chart (MSC) time Process 1Process 2Process 3 fm 1 fm 2 fm 4 fr 0 fr 1 fs 0 Core 1Core 2 task Message communication

6. Different cores conflict in L2 Shared cache. L2 Cache Set 0 Set 1 Set 2 Set 3 Core 1Core 2 Process 1Process 2Process 3 fm 1 fm 2 fm 4 fr 0 fr 1 fs 0 m m’ concurrent

7. J. Yan and W. Zhang RTAS 2008 –T, T’ are from different cores and they conflict for cache set C. –All the accesses from T and T’ to C are cache misses in the worst case. L2 Cache Set C - 1 Set C Set C + 1 Core 2 m 1, …, m k m’ 1, …, m’ k misses Core 1 Process 1 fm 1 fm 2 fm 4 Process2Process3 fr 0 fr 1 fs 0

8. Task Execution Lifetime Core 1Core 2 Start time End time Scenario 1: overlap lifetime conflicts Core 1Core 2 Start time End time Scenario 2: disjoint lifetime No conflicts Task 1 Task 2Task 1Task 2

9. yes no Estimated WCRT Intra Core Cache Analysis Core 1 Initial task interference Intra Core Cache Analysis Core n L2 cache conflict analysis WCRT Analysis Task Interference changes ? ……

10. yes no Estimated WCRT Initial task interference Modified task interference L2 cache conflict analysis WCRT Analysis Interference changes ? Intra Core Cache Analysis Core n …… Intra Core Cache Analysis Core 1

11. Must Analysis: Always Hit (AH) –Memory blocks guaranteed to be present in the cache May Analysis: Always Miss (AM) –Memory blocks may be present in the cache. Persistence Analysis –Never evicted from cache after first iteration. Others: Non Classified (NC) H. Theiling, C. Ferdinand. and R. Wilheml. Fast and precise WCET prediction by separated cache and path analyses. RTS 2000.

12. L1 Intra-core Cache Analysis. −Always Hit (AH), Always Miss (AM), Non Classified (NC) L2 Intra-core Cache Analysis AH AM NC L2 cache analysis L1 cache analysis AH AM NC accessnot access

13. yes no Estimated WCRT Intra Core Cache Analysis Core 1 Initial task interference Modified task interference Intra Core Cache Analysis Core 2 L2 cache conflict analysis WCRT Analysis Interference changes ?

14. Initial Task interference graph

15. Analyze each cache set individually Intra core L2 analysis – Always miss – Non classified – Always hit Set i Set j Task T m 0, m 1 m 2, m 3 conflicting tasks m’ 0, m’ 1 Non classified Always hit L2 cache

16. Consider memory block age: LRU replacement – age(m): maximal/upper bound of age of m. m0m0 m1m1 Age: 1 2 3 4 Task T m2m2 Always hit m’ 0, m’ 1 Conflicting tasks m0m0 m1m1 Age: 1 2 3 4 w/o optimization m2m2 Non classified m0m0 m1m1 Age: 1 2 3 4 with optimization m2m2 Always hit Non classified 2 memory blocks

17. yes no Estimated WCRT Intra Core Cache Analysis Core 1 Initial task interference Modified task interference Intra Core Cache Analysis Core 2 L2 cache conflict analysis WCRT Analysis Interference changes ?

18. L1 cacheL2 cacheBest-CaseWorst-Case AH---L1 hit AMAHL2 hit AM L2 miss AMNCL2 hitL2 miss NCAHL1 hitL2 hit NCAML1 hitL2 miss NC L1 hitL2 miss BCET and WCET Access Latency for best case and worst case. –Assumption: no timing anomalies with other architecture features Shortest (longest) path

19. Compute earliest, latest ready and finish time

20. Initial task interference L2 cache conflict analysis and WCRT analysis Interference graph Estimated WCRT Change ? Yes No

21. Cache access latency – L1 hit: 1 cycle, L2 hit: 10 cycle, Memory access: 100 cycle Various core numbers – 1 core, 2 cores and 4 cores Various cache configurations – cache size, block size, associativity Real-World Benchmarks: DEBIE.

22. Space Debris Monitoring Software 8 MSC, 35 tasks.

23. Comparison with Yan-Zhang RTAS 2008. Direct mapped cache only. (a) WCRT Comparison(b) Inter-core Eviction Comparison

24. Vary L1 and L2 Size. (a) Varying L1 Size (b) Varying L2 Size

25. Set associative cache optimizations m0m0 m1m1 w/o optimization m2m2 m0m0 m1m1 m2m2 Non classified Always hit Non classified Age: 1 2 3 4

26. Runtime of our iterative analysis

27. WCRT analysis of concurrent programs running on Shared cache multi-cores. Use task lifetime to indentify real conflicts. Optimizations for set associative cache. Experiments: tighter WCET than state of the art. Future work: data cache, other replacement policy

28. Thank You!