1. Unit-III Pipelined Architecture

2. Basic instruction cycle 6/4/2016MDS_SCOE_UNIT32

3. Instruction execution Every instruction requires five steps to execute The instruction Fetch (IF) The Instruction Decode (ID) The Execution (EX) The Memory and IO (MEM) The Write Back (WB) Pipelined and Non-pipelined concepts. 6/4/2016MDS_SCOE_UNIT33

4. Instruction execution Pipelining is the process of fetching the next instruction when the current instruction is being executed. 80386 Microprocessor supports pipelined arch that allows simultaneous instruction fetching,decoding,execution and MM. Reduced bus bandwidth,execution time,translation mechanism. Improved processor performance. 6/4/2016MDS_SCOE_UNIT34

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6. 80386DX Bus Cycles Collectively the address bus data bus and all associated control signals are referred to simply as ‘‘The Bus’’ The activity performing by microprocessor to access data from memory or I/O devices is called as a Bus Cycle. 6/4/2016MDS_SCOE_UNIT36

7. Bus Cycles and Bus States Bus State-the shortest time of the activity of the processor bus. It is one processor clock period in duration. Internal and external bus operations are synchronized with the clock(CLK) signal. 6/4/2016MDS_SCOE_UNIT37

8. Clock synchronizes all CPU and BUS operations machine (clock) cycle measures time of a single operation clock is used to trigger events 6/4/2016MDS_SCOE_UNIT38 Basic unit of time, 1GHz → clock cycle=1ns An instruction could take multiple cycles to complete, e.g. multiply in 8088 takes 50 cycles

9. 80386 specifics – External clock input signal CLK2: clock input – Internal processor clock(PCLK) signal : ½ frequency of CLK2 – Valid internal frequencies for different 80386 models: 16, 20, 25, 33 MHz – One (internal) cycle: 1 “T state” The clock signal that is applied to the CLK2 input of 80386DX is twice the frequency rating of the microprocessor. 6/4/2016MDS_SCOE_UNIT39

10. System clock Used to synchronize both internal and external operations Generated by external oscillator Specified in terms of frequency – Cycle time = 1 / frequency – Each CLK2 period is a phase of the internal clock. eg. In a 20 MHz 80386DX system,CLK2 frequency equals 40MHz. – Each clock cycle has a duration of 25ns(1/40MHz). » So processor clock period is 50 ns. 6/4/2016MDS_SCOE_UNIT310

11. 6/4/2016MDS_SCOE_UNIT311 Fig. Processor clock periods(bus states)

12. Bus state transition diagram. 6/4/2016MDS_SCOE_UNIT312

13. As shown in fig.each cycle has two states T1 and T2. Each state has two phases or two clock cycles. In T1 address and bus status pins are active and in T2 the data transfer will occure. If the 80386 does not need any bus cycles, it remains in the TI idle bus state. TI indicates that no bus cycle is currently being processed. Cycle starts after H/W reset. 6/4/2016MDS_SCOE_UNIT313

14. Bus Cycles/Operations  Interrupt acknowledge cycle  Memory read cycle  Memory write cycle  I/O read cycle  I/O write cycle  Instruction fetch cycle  Halt or shut down cycle 6/4/2016MDS_SCOE_UNIT314

15. Bus cycle definition signals M/IO# D/C# W/R# LOCK# -used during DMA access it indicates that the control of buses are locked and cannot be transferred to another processor till the next instruction. NA# - NEXT ADDRESS is used to output the address of next instruction or data in the current bus cycle before end of execution,used for pipelining of address. 6/4/2016MDS_SCOE_UNIT315

16. ADS#: The address status output pin indicates that the address bus and bus cycle definition pins( W/R#, D/C#, M/IO#, BE0# to BE3# ) are carrying the respective valid signals. The 80386 does not have any ALE signals and so this signals may be used for latching the address to external latches. READY#: The ready signals indicates to the CPU that the previous bus cycle has been terminated and the bus is ready for the next cycle. The signal is used to insert WAIT states in a bus cycle and is useful for interfacing of slow devices with CPU. 6/4/2016MDS_SCOE_UNIT316

17. BS16#: The bus size – 16 input pin allows the interfacing of 16 bit devices with the 32 bit wide 80386 data bus. Successive 16 bit bus cycles may be executed to read a 32 bit data from a peripheral. 6/4/2016MDS_SCOE_UNIT317

18. Bus states 6/4/2016MDS_SCOE_UNIT318

19. Non-pipelined bus cycle 6/4/2016MDS_SCOE_UNIT319

20. during T1 80386Dx outputs the address of the memory or I/O location that is to be accessed. During T2 external devices memory or I/O accept or put data on the bus(either write or read operation) In fig. address n is being output on the add bus in T1. it is available on the add bus throught T2 state. The data transfer for add n will take place in clock state T2. method requires four CLK2 cycles=100ns (80386 with 40MHz CLK2) 6/4/2016MDS_SCOE_UNIT320

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22. Pipelined bus cycle 6/4/2016MDS_SCOE_UNIT322

23. The add n becomes valid in the T2 state of previous bus cycle. The data transfer for an add n takes place in the next T2 state. At the same time the data transfer n occurs and add n+1 is output on the add bus. MP starts addressing the next mem/IO while it is performing read or write operation for previous address. This pipelined address method requires five CLK2 cycles=125ns (80386 with 40MHz CLK2) Ie. Here increased add-to-data access time. 6/4/2016MDS_SCOE_UNIT323

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25. 6/4/2016MDS_SCOE_UNIT325 Idle state cycle

26. In previous case we seen that after completion of the bus cycle for an add n another bus cycle is initiated immediately for the addr n+1. in some conditions it will not initiate immediately Eg. If prfetch queue is full and current instruction does not need to access any operand from memory, then no activity will take place and bus enters into a state called as idle state. There may several idle states in between bus cycle for addresses n+1 and n+2. the duration of single idle state is 2 CLK2 cycles. 6/4/2016MDS_SCOE_UNIT326

27. Idle state cycle 6/4/2016MDS_SCOE_UNIT327

28. 6/4/2016MDS_SCOE_UNIT328 Wait state cycle

29. Necessary to extend duration of 80386DX bus cycle. READY# signal is used to insert wait states This input is sampled in the later part of T2 state of every bus cycle to determine the completion of data transfer. READY#=1 indicates that the current bus cycle is not completed. Ie.the read or write operation does not take place and the current T2 state becomes a wait state(TW) to extend the bus cycle. External H/W returns signal READY#=0 and bus cycle goes into t2 state. 6/4/2016MDS_SCOE_UNIT329

30. Wait state cycle 6/4/2016MDS_SCOE_UNIT330

31. Classification of Cycles  Non – pipelined a) Non – pipelined READ cycle b) Non – pipelined WRITE cycle  Pipelined a) Pipelined READ/WRITE cycle  Interrupt acknowledged cycle  Complete Bus states  HALT / shutdown cycle 6/4/2016MDS_SCOE_UNIT331

32. Non-pipelined Read bus Cycle 6/4/2016MDS_SCOE_UNIT332

33. 1. The read operation starts in phase 1 of T1 state. During that time processor outputs 32bit address on address lines A2-A31,bus enable signals BE0-BE3 to identify bytes of the double word to be fetched,and switches ADS#=0 to indicate valid add is available on address bus. 2. Bus cycle definition signals M/IO#,D/C# and W/R# activates in the beginning of phase 1 of T1 state. There are two possible memory and IO read cycles 1.memory code read=100 2.memory data read=110 and 1.IO code read=000 2.IO data read=010 6/4/2016MDS_SCOE_UNIT333

34. 3. the add and bus defn cycle signals are maintained stable during the complete bus cycle. 4. At the beginning of phase1 in T2,the bus width of cycle gives by external h/w,as BS16#input signal. In the middle of phase 1 of T2 state 80386DX samples this signal. And in phase 2 of the T2 state 80386 does the data transfer. 6/4/2016MDS_SCOE_UNIT334

35. 5. READY# input signal is tested at the end of phase 2 of T2 state. If no wait state then data is available at the end of T2. In cycle 1 no wait state so data is available at T2.in cycle 2 one wait state is available so after ready# =0 data is available at the T2. If the lock#signal is asserted low then it indicates that the bus cycle is locked other master cannot use the bus. 6/4/2016MDS_SCOE_UNIT335

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37. Non-Pipelined Write cycle 6/4/2016MDS_SCOE_UNIT337

38. 1.In T1 state Outputs address, bus enable signals active 2.Bus cycle defn signals active. W/R# signal is active high indicating Write operation. 3.Processor outputs data to be written on the data bus at the beginning of phase 2 of T1 state. Data remains valid until the end of bus cycle. data must be latched to external circuitry when ADS#=0. at the end of phase 2 of T1 state ADS# signal becomes anactive 4. BS16# signal decides width of bus cycle 5. Finally at the end of phase 2 of the T2 state,READY# signal goes low to complete the bus cycle. 6/4/2016MDS_SCOE_UNIT338

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40. Pipelined Read and Write Cycles 6/4/2016MDS_SCOE_UNIT340

41. NA# signal is used to achive pipelining of addresses. NA# input is sampled at the end of phase 1 of every T2 state. For NA# to be sampled,BS16# must be logic 1. If NA# and BS16# are both sampled asserted then current bus size is taken to be 16 and next address is not pipelined. NA# is first tested to 0 during T2 of cycle 2. 6/4/2016MDS_SCOE_UNIT341

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43. Interrupt Acknowledge Bus Cycle 6/4/2016MDS_SCOE_UNIT343

44. It is used to activate INTA# signal for the PIC. 80386DX executes intrrupt ack cycle to read an interrupt from an external inetrrupt controller(PIC 8259) Fig shows 2 cycles,needed to maintain the pulse width requirements of the interrupt controller. 1. in phase 1 of T1 state Processor sets the add lines A3 to A31.the BE0#=0 and A2=1,BE1# to BE3#=1 6/4/2016MDS_SCOE_UNIT344

45. 2. In this phase 386 also sets the bus definition signals M/IO#,D/C# and W/R#=0 to generate INTA# signal. - these signals are latched to the external devices with ADS# signal. 3. In the second INTA# cycle,all above signals are activated except A2 made to logic 0.LOCK# is activated at the starting of 1st cycle to the end of 2nd cycle so that bus is locked. 4. The inputs are ignored in both the cycles. The int number is read by the processor in the phase 2 of the T2 state on the data lines D0-D7 6/4/2016MDS_SCOE_UNIT345

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47. Halt/Shutdown Cycle Whenever a HALT instruction is executed,the 80386DX goestion remain into a halt condition. When a double fault is being processed and a protection fault is being found the shutdown condition occurs. Shutdown/halt condition remains till NMI =1 or RESET=1 6/4/2016MDS_SCOE_UNIT347

48. Halt/Shutdown Cycle The cycle is activated by initiating ADS# signal and the Bus status signals. The M/IO#,W/R# are driven high and D/C# is driven low to indicate a halt cycle. All addresses are set to logic 0. BE0# is active for a shutdown condition and BE2# is active for a halt condition. 6/4/2016MDS_SCOE_UNIT348

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50. Bus Lock Cycle Used in multiprocessor system Mutual exclusion semaphores 6/4/2016MDS_SCOE_UNIT350

51. Complete bus states 6/4/2016MDS_SCOE_UNIT351