Presentation on theme: "V850/Jx4 Series Ultra Low Power 32 bit MCUs Migration from V850/Jx3 MCUs Today we will cover migration from the the V850 Jx3 series of 32bit MCUs to the."— Presentation transcript:
2 Key Development Goals for the V850 Jx4 V850 J Series 32bit MCU Roadmap AgendaKey Development Goals for the V850 Jx4V850 J Series 32bit MCU RoadmapV850 Jx4 Enhancements over Jx3V850 Jx3 to Jx4 CompatibilityV850 Jx3-L to Jx4-L Pin out ComparisonComparison of Some PeripheralsHere is an agenda for today’s presentation(click)We will start by discussing the key development goals for the V850 Jx4 Series of ProductsThen we will review the roadmap for our V850 J Series MCUsWe will examine the Jx4 Enhancements over the Jx3Then, review to compatibility between the two seriesWe will review a pinout comparision for the Jx3-L and Jx4-L devicesAnd finally we will take a deeper comparison of a few peripherals
3 Jx4 Goals V850E2/Jx4 Series Goals Ultra Low Power Software Scalability 70%Down!1.23Power performance rate [mw/MIPS]Dhy.2.11.07Jx3-LJx4-LA87%Down!14Standby current (RAM hold) [mA]1.5Software Scalability200MHz, Dual32MHz60DMIPS64MHz120MHz300DMIPS1000MIPSCompact & Small0.75mm thicknessFBGA64pin113pin8x85x5*QFP are standardLine-up176pin10x1048pin40pinWQFN9x97x76x640pin 48pin 64pin 80pin 100pin 128pin 144pin 176pin2MB1.5MB1MB768KB512KB384KB256KB128KB64KB32KBJx4-L@32MHzJx4@64MHzBroad ScalabilityThere are development goals for the Jx4 series.(click)First, a significant power reduction from Jx3 products both in normal operation as well as in various power down modes.Second, software scalability from V850 products with a wide range of cores from 32MHz all the way to 200 MHz with dual cores.Standard packages that are compact in length and width but also with thickness for small battery power devicesFinally, a tremendous range of Flash Memory sizes from 32KB to 2MB as well as pin counts from 40 to 176 pins to provide designers to standardize on the Jx4 as a platform for many different solutions.
4 Increased Functionality V850-J Series Road mapExpansion of line-up in V850 Jx3 seriesJx4 seriesConnectivityLow pinV850ES/Jx3-EJx3-E LPCEthernet 50MHzBasicK/124-76K128/144pin256-64K/64-32K64/80/100pinJx4Low pinV850ES/Jx3-H/-UJx3-H LPCUSB 48MHzHigher performanceUltra low powerUSB in every deviceIncreased FunctionalityK/56K-40K100/128pin256-16K/24-8K40/48/64pinLow powerV850ES/Jx3Standard 32MHzThe V850 supports an extremely wide range of product families, each is categorized in a particular series . The J Series provides a combination of high-performance processing power with low power consumption for battery power applications.The existing Jx3 series of products include support for two broad categories of solutions, connectivity and low power. Much of the recent success of the Jx3 has been in battery power applications using the low power series of products.(click)Enter the next generation Jx4 series. There will be two different families of Jx4 products, the Jx4-L low power the Jx4 basic lines. We will go into more detail throughout the rest of the presentation.Some key enhancements include higher performance, up to 61 DMIPS for the Jx4-L vs. 43 DMIPs for the Jx3-L and 116 DMIPs for the Jx4 series vs 98 DMIPs for the Jx3.Power consumption has been reduced in virtually any operating modeUSB function is now standard in every Jx4 series device with USB host supported in some of the Jx4 Basic devicesMore functionality has been incorporated into each product resulting in an overall expansion of the Jx3 product line1M-384K/60-32K100/144pinJx3-LMELow powerJx4-LPin Compatibility1M-256K/80-32K100pinV850ES/Jx3-LLow Power 20MHzLow pinJx3-LLPCK/16-8K80/100pin256K-16K/16K-8K40/48/64pin
5 Summary of Enhancements in Jx4-L vs. Jx3-L V850ES/Jx3-LV850E2/Jx4-LPointCPU CoreV850ESV850E2SCPU is upward compatibleMax.Freq./Performance(Dhy2.1)20MHz/38MIPSMore PerformanceInternal Flash16K-1MB32K-2MBLarge memory/wide variations line-upInternal RAM8K-80KB8K-128KBData FlashNone16-32KBInstead of external EEPROMOperating voltage2.7V to2.2V to2.0V to2.7V to1.8V to1.6V toLow voltage operationMin.1.6VInternal OSC (for Main)N/A32MHz ;±1%accuracyReduce external clockRTC N/A or ○:Independent (VDD/RVDD)○: Normal (VDD)Low power in STOP(RAM hold)USB2.0N/A or Function x 1ch (FS)Function x 1ch (FS/LS)USB Function on All DevicesNow we would like to provide you a summary of the major enhancements of the Jx4-L over the Jx3-L(click) The CPU core is now the V850E2S vs. the V850ES. The new core is upward compatible(click) More performance by improving the operating frequency from 20MHz to 32MHz with the same efficiency(click) Both smaller and larger Flash up to 2MB and RAM up to 128KB for more flexibility(click) Data Flash added so no external EEPROM is required(click) Low voltage operation extend to 1.6V minimum(click) RTC added in Jx4-L(click) USB 2.0 Full Speed Function available on all Jx4-L devices(click) Power on Reset added(click) A/D supports lower 1.6V operation as well as 12 bits, up from 10 bits(click) Ultra low power improved in every operating mode(click) Some larger packages addedPOR/LVDN/A or ○(2.1V/2.3V/2.8V)○(1.51V)/○( V)Add POR, enhance LVDA/D converter10 bits x 5-12ch, Min.2.7V, 2us12bitsx5-24ch, Min.1.6V, 1usLow voltage operation 1.6V~Run12mA(20MHz, 3.3V)6mA(32MHz, 3.3V) *3.5mA(16MHz, 3.3V) *Realize Ultra low powerConsumption currentSTOP+RTC*Backup modeN/APackage40pin to 121pinLQFP/WQFN/FBGA40pin to 144pinLQFP/WQFN/FBGALPC, PKG line-up* Target specification
6 Enhanced V850 CPU coreThe V850E2S (Jx4) core is upward compatible from the V850ES (Jx3)CPU CoreV850ESV850E2SV850E2MCore Max Freq.50MHz~64MHz~266MHzPerformance(DMIPS 2.1)1.9DMIPS/MHz2.56DMIPS/MHzPipeline5-stage7-stage+ Load/Branch pipe+ Non-block load/store+ Dual execution+ FPU Single/Duble accuracyDedicatedHW Multiplier/MAC16x1632x3232x (MAC)InstructionMixed of RISC + CSCI+ C-compatible Switch instruction+ Data conversion instruction and etc+ Bit Search Instruction+ Sum-of-Product Instruction+ 32-bit relative branchThe V850 Jx4 uses the latest V850E2S core which is completely upward compatible with the V850ES core used in the Jx3. Any software that you have developed for the Jx3 will work on the Jx4.Both cores are highly efficient producing a high 1.9DMIPs/MHz performance. The new V850E2S core can support a higher 64MHz maximum frequency, improved over the 50MHz in the V850ES.A few instructions have been added to the core including (click) two 64 bit Multiply Accumulate or MAC instructions as well as (click) a two bit search instructions, a sum-of-product instruction and a number of 32bit relative branch instructions.6
7 Compatibility of Jx4-L and Jx3-L ○ :Compatibility (same IP)△ :Function compatibility &additional function× :No compatibilityCompatibility of Jx4-L and Jx3-LV850ES/JG3-LV850E2/Jx4-LCompatibilityRemarkCPUV850ESV850E2S○Instruction upper compatibilityTimer/CounterTMP/TMQ/TMMTAU/TMM×/○TMM has compatibilityReal time counterRTCRTC○No independent power supply/ Backup modeWacthdog timerWDT2WWDT△Window width (25/50/75/100%) settingSerial I/FCSIB/UARTA/I2CSAU/I2C×/○SAU : CSI/UART, I2C has compatibilityUSB2.0 controllerUSBF(FS)USBF(FS/LS)△Supported USB class are same(CDC/HID/MSC/etc.)DMA controller4ch8ch○Transfer times:65536 to 32768,add transfer modeAD converter10bit12bit△Scan mode specification changeDA converter8bit8bit○Key return functionKRKR○Real time outputRTORTO○CRC circuitThis table gives a brief comparison of the compatibility between the Jx4-L and Jx3-L. We are indicating compatibility as follows: circle means same IP therefore fully compatible, triangle means functional compatibility as well as additional features, x means no compatibility. As you can see, most of the functions in the products are either the same IP or functionally compatible.The areas that have changed include the timer/counters, SCI and UART as well as a change in register port setting for the general purpose port. These features are clearly document and we provide detailed information to simplify migration from one to the other.CRCCRC○Clock monitorCLMCLM○Internal OSC : change 220kHz to 15kHzClock/Buzzer outputN/A○NewPower on clear (POR)N/A○ (1.51V)NewLow voltage detect(LVD)Internal : 2.0/2.3/2.7VExternal : :N/AInternal : VExternal : 1.8 to 2.9V△External bus I/FSeparate/MultiSeparate/Multi○Change for AC specGeneral purpose PortInput/OutputInput/Output×Change for specification about port setting resisterStand-by functionHALT/IDLE/STOPHALT/STOP/SNOOZE△SNOOZE mode is newOn-chip debagJTAG I/F (5pin )NEXUS I/F (6pin)○NEXUS : JTAG upper compatible
8 V850 Jx3-L to Jx4-L Pin Compatibility V850ES/JG3-L and V850E2/JG4-L pinoutThe pinout is not compatible due toMany new features requiring support for new pinsInternal power supply routingPeripheral setAnalog functionRenesas will provide guidelines to migrate from one product line to the otherAlthough pin compatibility is always a desired feature, there is no pinout compatibility between two primarily do to a large increase in new functionality in the Jx4-L. Also, there were changes to the internal power supply routing, enhancements to the peripheral set as well as changes to the analog functions.Renesas will provide detailed guidelines to migrate from Jx3 to Jx4
9 Pinout of V850ES/JG3-L to V850E2/JG4-L analogclockpowerAddr/DataperipheralThis page shows a quick comparison of two similar products. Although it is a bit difficult to see all of the pins in this diagram, you can see by the various color sections that functional blocks have been moved to allow for the new features supported with the Jx4-LRenesas will provide more details to simplify the migration process from Jx3-L to the Jx4-L.
10 DMA controller Function Jx3-L Jx4-L/Jx4 Channel 4ch 8ch Transfer unit 8bit/16bit8bit/16bit/32bitMaximum transfer count6553632768Transfer type2 cycle transfer<---Transfer modeSingle transferSingle step transferTransfer requestsInternal peripheral /OExternal InterruptSoftware triggerTransfer targetsInternal RAMInternal peripheral I/OExternal memoryInternal Flash(read only)Data Flash(read only)The DMA Controller is compatible with just a few changes(click) Support for 32 bit transfer units(click) A lower maximum transfer count(click) Some new transfer targets
11 External bus interface FunctionV850ES/Jx3-LV850E2/Jx4-L, Jx4Bus typeMultiplex/Separate<---Address bus24 bit23 bitData bus8/16 bit<---Bus clock dividerN.ASupported (fxx/2, 4, 8)Chip select output4<---Data endian functionN.ASupported(Little/Big endian selectable every CS)Programmable waitData: DataAddress: Setup/HoldData: Data/HoldAddress: Setup/HoldExternal waitThe External bus interface is functionally compatibleSome of the changes have been made in the following:(click)One less address bitBus clock can be divided by 2,4 and 8Added Little/Big endian selectable ever CS)(click) One more wait state(click) No more bus hold functionSupported<---Idle state insert functionSupported (1cycle)Supported(1 to 2 cycle)Endian typeLittle endian<---Misaligned data accessSupported<---Bus hold functionSupportedN.A11
12 Timer/Counter TAU (Timer Array Unit) has flexibility of a function Jx3-LJx3-H/-EJx4-LJx416bit General purpose timerTMPTMQTAATABTAUR(Timer Array Unit)Motor control timer－TAB+TMQOP16bit Encode timerTMTENCA16bit Interval timerTMMTAURInterval timerExternal event counterExternal trigger pulse outputOne-shot pulse outputPWM outputPulse width measurementThe primary difference with the Timers is the addition of a Timer Array unit. This new array provides a wide range of timers useful for a range of various applications.
13 Window Watch Dog Timer Default-start watchdog timer Reset mode: Reset operation upon overflow of watchdog timer (generation of WDTRES signal)Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer (generation of INTWDT2 signal)Input from main clock, internal oscillation clock, and sub-clock selectable as the source clockWindow size selectable:25/50/75/100%Window opening period: writing of a WDTE register is effective, and reset a counterWindow closing period: writing of a WDTE register to be unusual detection, and reset CPUSelector18bits counterRESETOutputcontrolStandbyWindow sizecheckInterval timeControlWriting detection(click) The Watch Dog Timer has been enhanced to provide a selectable window size. Other than this enhancement, this is fully compatible with WDT on the Jx3 series
14 Serial I/F SAU(Serial Array Unit) can choose CSI/UART freely SAU04R FunctionJx3-LJx3-HJx3-EJx4-LJx4CSIFunc.CSIBCSIFCSIE(w/FIFO)SAU02SSAU02R/04RSpeed8Mbps8/12Mbps5/8Mbps8/16MbpsUARTUARTAUARTC(9bit)UARTC(9bit)UARTB(w/FIFO)625Kbps3Mbps3.125Mbps5.3MbpsI2C100/400Kbps<----100K/400K/1MbpsFor the Serial Ports, we have added support for a Serial Array unit which provides similar functionality as before but in an array.Much of the enhancements include support for higher speeds.For example, (click) the CSI now supports up to 16MbpsThe UART supports up to (click) 5.3Mbps for Jx4-L and (click) 8Mbps for Jx4I2C now supports up (click) 1MbpsSAU04RSAU02S
15 Key Development Goals for the V850 Jx4 SummaryKey Development Goals for the V850 Jx4Ultra Low PowerSoftware CompatibilityCompact and SmallBroad ScalabilityV850 Jx4 Enhancements over Jx3V850 Jx3 to Jx4 CompatibilityMigration is simple and straightforwardSoftware is upwardly compatibleMuch of the IP is the same or has enhanced functionality that is compatibleThank you for listening to today’s presentation.In summary,(click)We reviewed the key development goals for the V850 Jx4 including ultra low power, software compatibility with many V850 devices, Compact and small packages as well as broad scalability of Flash from 32KB to 2MB and a wide range of package typesThen we reviewed the large number of enhancements over the Jx3Finally, we demonstrated that is a simple and straightforward process of migrating from a Jx3 solution to Jx4. In fact, all of your Jx3 software is upward compatible and many of the IP is the same or a superset of existing functionality.For more information on the Renesas V850 lineup and features, please view the other V850 courses, here on Renesas InteractiveThank you for your time an interest.