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V850/Jx4 Series Ultra Low Power 32 bit MCUs Migration from V850/Jx3 MCUs Today we will cover migration from the the V850 Jx3 series of 32bit MCUs to the.

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Presentation on theme: "V850/Jx4 Series Ultra Low Power 32 bit MCUs Migration from V850/Jx3 MCUs Today we will cover migration from the the V850 Jx3 series of 32bit MCUs to the."— Presentation transcript:

1 V850/Jx4 Series Ultra Low Power 32 bit MCUs Migration from V850/Jx3 MCUs
Today we will cover migration from the the V850 Jx3 series of 32bit MCUs to the Jx4 Series. The J Series provides a combination of high-performance processing power with low power consumption for battery power applications. March 2012 © 2011 Renesas Electronics Corporation. All rights reserved.

2 Key Development Goals for the V850 Jx4 V850 J Series 32bit MCU Roadmap
Agenda Key Development Goals for the V850 Jx4 V850 J Series 32bit MCU Roadmap V850 Jx4 Enhancements over Jx3 V850 Jx3 to Jx4 Compatibility V850 Jx3-L to Jx4-L Pin out Comparison Comparison of Some Peripherals Here is an agenda for today’s presentation (click) We will start by discussing the key development goals for the V850 Jx4 Series of Products Then we will review the roadmap for our V850 J Series MCUs We will examine the Jx4 Enhancements over the Jx3 Then, review to compatibility between the two series We will review a pinout comparision for the Jx3-L and Jx4-L devices And finally we will take a deeper comparison of a few peripherals

3 Jx4 Goals V850E2/Jx4 Series Goals Ultra Low Power Software Scalability
70%Down! 1.23 Power performance rate [mw/MIPS] Dhy.2.1 1.07 Jx3-L Jx4-L A 87%Down! 14 Standby current (RAM hold) [mA] 1.5 Software Scalability 200MHz, Dual 32MHz 60DMIPS 64MHz 120MHz 300DMIPS 1000MIPS Compact & Small 0.75mm thickness FBGA 64pin 113pin 8x8 5x5 *QFP are standard Line-up 176pin 10x10 48pin 40pin WQFN 9x9 7x7 6x6 40pin 48pin 64pin 80pin 100pin 128pin 144pin 176pin 2MB 1.5MB 1MB 768KB 512KB 384KB 256KB 128KB 64KB 32KB Jx4-L @32MHz Jx4 @64MHz Broad Scalability There are development goals for the Jx4 series. (click) First, a significant power reduction from Jx3 products both in normal operation as well as in various power down modes. Second, software scalability from V850 products with a wide range of cores from 32MHz all the way to 200 MHz with dual cores. Standard packages that are compact in length and width but also with thickness for small battery power devices Finally, a tremendous range of Flash Memory sizes from 32KB to 2MB as well as pin counts from 40 to 176 pins to provide designers to standardize on the Jx4 as a platform for many different solutions.

4 Increased Functionality
V850-J Series Road map Expansion of line-up in V850 Jx3 series Jx4 series Connectivity Low pin V850ES/ Jx3-E Jx3-E LPC Ethernet 50MHz Basic K/124-76K 128/144pin 256-64K/64-32K 64/80/100pin Jx4 Low pin V850ES/ Jx3-H/-U Jx3-H LPC USB 48MHz Higher performance Ultra low power USB in every device Increased Functionality K/56K-40K 100/128pin 256-16K/24-8K 40/48/64pin Low power V850ES/ Jx3 Standard 32MHz The V850 supports an extremely wide range of product families, each is categorized in a particular series . The J Series provides a combination of high-performance processing power with low power consumption for battery power applications. The existing Jx3 series of products include support for two broad categories of solutions, connectivity and low power. Much of the recent success of the Jx3 has been in battery power applications using the low power series of products. (click) Enter the next generation Jx4 series. There will be two different families of Jx4 products, the Jx4-L low power the Jx4 basic lines. We will go into more detail throughout the rest of the presentation. Some key enhancements include higher performance, up to 61 DMIPS for the Jx4-L vs. 43 DMIPs for the Jx3-L and 116 DMIPs for the Jx4 series vs 98 DMIPs for the Jx3. Power consumption has been reduced in virtually any operating mode USB function is now standard in every Jx4 series device with USB host supported in some of the Jx4 Basic devices More functionality has been incorporated into each product resulting in an overall expansion of the Jx3 product line 1M-384K/60-32K 100/144pin Jx3-L ME Low power Jx4-L Pin Compatibility 1M-256K/80-32K 100pin V850ES/ Jx3-L Low Power 20MHz Low pin Jx3-L LPC K/16-8K 80/100pin 256K-16K/16K-8K 40/48/64pin

5 Summary of Enhancements in Jx4-L vs. Jx3-L
V850ES/Jx3-L V850E2/Jx4-L Point CPU Core V850ES V850E2S CPU is upward compatible Max.Freq./Performance (Dhy2.1) 20MHz/38MIPS More Performance Internal Flash 16K-1MB 32K-2MB Large memory/wide variations line-up Internal RAM 8K-80KB 8K-128KB Data Flash None 16-32KB Instead of external EEPROM Operating voltage 2.7V to 2.2V to 2.0V to 2.7V to 1.8V to 1.6V to Low voltage operation Min.1.6V Internal OSC (for Main) N/A 32MHz ;±1%accuracy Reduce external clock RTC  N/A or ○:Independent (VDD/RVDD) ○: Normal (VDD) Low power in STOP(RAM hold) USB2.0 N/A or Function x 1ch (FS) Function x 1ch (FS/LS) USB Function on All Devices Now we would like to provide you a summary of the major enhancements of the Jx4-L over the Jx3-L (click) The CPU core is now the V850E2S vs. the V850ES. The new core is upward compatible (click) More performance by improving the operating frequency from 20MHz to 32MHz with the same efficiency (click) Both smaller and larger Flash up to 2MB and RAM up to 128KB for more flexibility (click) Data Flash added so no external EEPROM is required (click) Low voltage operation extend to 1.6V minimum (click) RTC added in Jx4-L (click) USB 2.0 Full Speed Function available on all Jx4-L devices (click) Power on Reset added (click) A/D supports lower 1.6V operation as well as 12 bits, up from 10 bits (click) Ultra low power improved in every operating mode (click) Some larger packages added POR/LVD N/A or ○(2.1V/2.3V/2.8V) ○(1.51V)/○( V) Add POR, enhance LVD A/D converter 10 bits x 5-12ch, Min.2.7V, 2us 12bitsx5-24ch, Min.1.6V, 1us Low voltage operation 1.6V~ Run 12mA(20MHz, 3.3V) 6mA(32MHz, 3.3V) * 3.5mA(16MHz, 3.3V) * Realize Ultra low power Consumption current STOP+RTC * Backup mode N/A Package 40pin to 121pin LQFP/WQFN/FBGA 40pin to 144pin LQFP/WQFN/FBGA LPC, PKG line-up * Target specification

6 Enhanced V850 CPU core The V850E2S (Jx4) core is upward compatible from the V850ES (Jx3) CPU Core V850ES V850E2S V850E2M Core Max Freq. 50MHz ~64MHz ~266MHz Performance (DMIPS 2.1) 1.9DMIPS/MHz 2.56DMIPS/MHz Pipeline 5-stage 7-stage + Load/Branch pipe + Non-block load/store + Dual execution + FPU Single/Duble accuracy Dedicated HW Multiplier/MAC 16x16 32x32 32x (MAC) Instruction Mixed of RISC + CSCI + C-compatible Switch instruction + Data conversion instruction and etc + Bit Search Instruction + Sum-of-Product Instruction + 32-bit relative branch The V850 Jx4 uses the latest V850E2S core which is completely upward compatible with the V850ES core used in the Jx3. Any software that you have developed for the Jx3 will work on the Jx4. Both cores are highly efficient producing a high 1.9DMIPs/MHz performance. The new V850E2S core can support a higher 64MHz maximum frequency, improved over the 50MHz in the V850ES. A few instructions have been added to the core including (click) two 64 bit Multiply Accumulate or MAC instructions as well as (click) a two bit search instructions, a sum-of-product instruction and a number of 32bit relative branch instructions. 6

7 Compatibility of Jx4-L and Jx3-L
○ :Compatibility (same IP) △ :Function compatibility & additional function × :No compatibility Compatibility of Jx4-L and Jx3-L V850ES/JG3-L V850E2/Jx4-L Compatibility Remark CPU V850ES V850E2S Instruction upper compatibility Timer/Counter TMP/TMQ/TMM TAU/TMM ×/○ TMM has compatibility Real time counter RTC RTC No independent power supply/ Backup mode Wacthdog timer WDT2 WWDT Window width (25/50/75/100%) setting Serial I/F CSIB/UARTA/I2C SAU/I2C ×/○ SAU : CSI/UART, I2C has compatibility USB2.0 controller USBF(FS) USBF(FS/LS) Supported USB class are same (CDC/HID/MSC/etc.) DMA controller 4ch 8ch Transfer times:65536 to 32768, add transfer mode AD converter 10bit 12bit Scan mode specification change DA converter 8bit 8bit Key return function KR KR Real time output RTO RTO CRC circuit This table gives a brief comparison of the compatibility between the Jx4-L and Jx3-L. We are indicating compatibility as follows: circle means same IP therefore fully compatible, triangle means functional compatibility as well as additional features, x means no compatibility. As you can see, most of the functions in the products are either the same IP or functionally compatible. The areas that have changed include the timer/counters, SCI and UART as well as a change in register port setting for the general purpose port. These features are clearly document and we provide detailed information to simplify migration from one to the other. CRC CRC Clock monitor CLM CLM Internal OSC : change 220kHz to 15kHz Clock/Buzzer output N/A New Power on clear (POR) N/A ○ (1.51V) New Low voltage detect (LVD) Internal : 2.0/2.3/2.7V External : :N/A Internal : V External : 1.8 to 2.9V External bus I/F Separate/Multi Separate/Multi Change for AC spec General purpose Port Input/Output Input/Output × Change for specification about port setting resister Stand-by function HALT/IDLE/STOP HALT/STOP/SNOOZE SNOOZE mode is new On-chip debag JTAG I/F (5pin ) NEXUS I/F (6pin) NEXUS : JTAG upper compatible

8 V850 Jx3-L to Jx4-L Pin Compatibility
V850ES/JG3-L and V850E2/JG4-L pinout The pinout is not compatible due to Many new features requiring support for new pins Internal power supply routing Peripheral set Analog function Renesas will provide guidelines to migrate from one product line to the other Although pin compatibility is always a desired feature, there is no pinout compatibility between two primarily do to a large increase in new functionality in the Jx4-L. Also, there were changes to the internal power supply routing, enhancements to the peripheral set as well as changes to the analog functions. Renesas will provide detailed guidelines to migrate from Jx3 to Jx4

9 Pinout of V850ES/JG3-L to V850E2/JG4-L
analog clock power Addr/Data peripheral This page shows a quick comparison of two similar products. Although it is a bit difficult to see all of the pins in this diagram, you can see by the various color sections that functional blocks have been moved to allow for the new features supported with the Jx4-L Renesas will provide more details to simplify the migration process from Jx3-L to the Jx4-L.

10 DMA controller Function Jx3-L Jx4-L/Jx4 Channel 4ch 8ch Transfer unit
8bit/16bit 8bit/16bit/32bit Maximum transfer count 65536 32768 Transfer type 2 cycle transfer <--- Transfer mode Single transfer Single step transfer Transfer requests Internal peripheral /O External Interrupt Software trigger Transfer targets Internal RAM Internal peripheral I/O External memory Internal Flash(read only) Data Flash(read only) The DMA Controller is compatible with just a few changes (click) Support for 32 bit transfer units (click) A lower maximum transfer count (click) Some new transfer targets

11 External bus interface
Function V850ES/Jx3-L V850E2/Jx4-L, Jx4 Bus type Multiplex/Separate <--- Address bus 24 bit 23 bit Data bus 8/16 bit <--- Bus clock divider N.A Supported (fxx/2, 4, 8) Chip select output 4 <--- Data endian function N.A Supported (Little/Big endian selectable every CS) Programmable wait Data: Data Address: Setup/Hold Data: Data/Hold Address: Setup/Hold External wait The External bus interface is functionally compatible Some of the changes have been made in the following: (click) One less address bit Bus clock can be divided by 2,4 and 8 Added Little/Big endian selectable ever CS) (click) One more wait state (click) No more bus hold function Supported <--- Idle state insert function Supported (1cycle) Supported(1 to 2 cycle) Endian type Little endian <--- Misaligned data access Supported <--- Bus hold function Supported N.A 11

12 Timer/Counter TAU (Timer Array Unit) has flexibility of a function
Jx3-L Jx3-H/-E Jx4-L Jx4 16bit General purpose timer TMP TMQ TAA TAB TAUR (Timer Array Unit) Motor control timer TAB+TMQOP 16bit Encode timer TMT ENCA 16bit Interval timer TMM TAUR Interval timer External event counter External trigger pulse output One-shot pulse output PWM output Pulse width measurement The primary difference with the Timers is the addition of a Timer Array unit. This new array provides a wide range of timers useful for a range of various applications.

13 Window Watch Dog Timer Default-start watchdog timer
Reset mode: Reset operation upon overflow of watchdog timer (generation of WDTRES signal) Non-maskable interrupt request mode: NMI operation upon overflow of watchdog timer (generation of INTWDT2 signal) Input from main clock, internal oscillation clock, and sub-clock selectable as the source clock Window size selectable:25/50/75/100% Window opening period: writing of a WDTE register is effective, and reset a counter Window closing period: writing of a WDTE register to be unusual detection, and reset CPU Selector 18bits counter RESETOutput control Standby Window size check Interval time Control Writing detection (click) The Watch Dog Timer has been enhanced to provide a selectable window size. Other than this enhancement, this is fully compatible with WDT on the Jx3 series

14 Serial I/F SAU(Serial Array Unit) can choose CSI/UART freely SAU04R
Function Jx3-L Jx3-H Jx3-E Jx4-L Jx4 CSI Func. CSIB CSIF CSIE(w/FIFO) SAU02S SAU02R/04R Speed 8Mbps 8/12Mbps 5/8Mbps 8/16Mbps UART UARTA UARTC(9bit) UARTC (9bit) UARTB(w/FIFO) 625Kbps 3Mbps 3.125Mbps 5.3Mbps I2C 100/400Kbps <---- 100K/400K/1Mbps For the Serial Ports, we have added support for a Serial Array unit which provides similar functionality as before but in an array. Much of the enhancements include support for higher speeds. For example, (click) the CSI now supports up to 16Mbps The UART supports up to (click) 5.3Mbps for Jx4-L and (click) 8Mbps for Jx4 I2C now supports up (click) 1Mbps SAU04R SAU02S

15 Key Development Goals for the V850 Jx4
Summary Key Development Goals for the V850 Jx4 Ultra Low Power Software Compatibility Compact and Small Broad Scalability V850 Jx4 Enhancements over Jx3 V850 Jx3 to Jx4 Compatibility Migration is simple and straightforward Software is upwardly compatible Much of the IP is the same or has enhanced functionality that is compatible Thank you for listening to today’s presentation. In summary, (click) We reviewed the key development goals for the V850 Jx4 including ultra low power, software compatibility with many V850 devices, Compact and small packages as well as broad scalability of Flash from 32KB to 2MB and a wide range of package types Then we reviewed the large number of enhancements over the Jx3 Finally, we demonstrated that is a simple and straightforward process of migrating from a Jx3 solution to Jx4. In fact, all of your Jx3 software is upward compatible and many of the IP is the same or a superset of existing functionality. For more information on the Renesas V850 lineup and features, please view the other V850 courses, here on Renesas Interactive Thank you for your time an interest.

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