1. Layout-Driven Test-Architecture Design and Optimization for 3D SoCs under Pre-Bond Test- Pin-Count Constraint Li Jiang 1, Qiang Xu 1, Krishnendu Chakrabarty 2, and T. M. Mak 3 1 Deptartment of CS&E, The Chinese University of Hong Kong, Shatin, N.T., Hong Kong 2 Deptartment of ECE, Duke University, Durham, NC 3 Intel Corporation, Santa Clara, CA

2. Outline Background Motivation Approach Experiments Conclusion

3. Background TSV Technique Benefit of 3D IC Interconnect Performance Power Memory Bandwidth Heterogeneous Integration 1. Gabriel H. Loh. 3D-Stacked Memory Architectures for Multi-Core Processors. ISCA. 2008

4. Background Pre-bond Test W2W Simplicity of the Manufacturing Process Low Yield D2D & D2W Pre-bond Test High Yield

5. Background Test Architecture Design IEEE P1500 Standard TAM Manner TSV Pad Additional Pad Primary Pad Routing Model TAM Segment

6. Background Test-Pin-Count Constraint Fine-grained Touchdown Probe Needles Unavailable Impossible to fabricate a large number of test pads for pre-bond testing Area of Pad Probe Force to the Thinned Wafer

7. Outline Introduction Motivation Approach Experiments Conclusion

8. Motivation Separate Test Architectures for Pre-bond Tests and Post-bond Test Share the Routing Resources

9. Problem Definition Given Set of Cores Test Parameters (Scan chain, Pattern, Input/Output) of each core Physical Position of Each Core Maximum available TAM width pre-bond test-pin-count constraintWpre; Determine Number of TAM Core Assignment Width of each TAM Objectivity minimize the total test cost

10. Total Test Cost Test Cost Model C total = C Test-Time * α+ C Wire-Length *(1- α) C Test-Time = C Test-Chip + Σ C Test-Layer C Wire-Length depends on routing model Routing Model Manhattan Distance TAM Segment TSP 3 3.S. Goel and E. Marinissen. Layout-driven SOC test architecture design for test time and wire length minimization. In Proceedings IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition, pages 738–743, 2003.

11. Outline Introduction Motivation Approach TAM Wire Reuse with Fixed Test Architectures TAM Wire Reuse with Flexible Pre-bond Test Architecture Experiments Conclusion

12. TAM Wire Reuse with Fixed Test Architectures Test Architecture Optimization for Both Post- bond Test and Pre-bond Test Fix the TAM (width, core assignment) Post-bond TAM Routing Identification of Reusable TAM Segments Pre-bond TAM Routing

13. TAM Wire Reuse with Fixed Test Architectures Post-bond TAM Routing Construct the Complete Graph Sort Edges Greedy Choose Update the Candidates Not TSP

14. TAM Wire Reuse with Fixed Test Architectures Identification of Reusable TAM Segments Manhattan Distance and Bounding Rectangles Overlapping Bounding Rectangles Impact of Relative Slope

15. TAM Wire Reuse with Fixed Test Architectures Pre-bond TAM Routing Get Possible Reusable Post-bond TAM Segments Construct Completed Graph G i for Every Pre-bond TAM in the layer, and put all G i together into SG. Build List for Each Pre-bond TAM Segment, Store All Possible Reusable Candidates into the List Combined with the Routing Cost after Reuse. Sort the list According to the Routing Cost In Every Iteration, Choose the Segment with Least Routing Cost Move it into EG Delete this Reused Segment from all other edges in SG Update the Candidate Segment Obtain the Routing Result and its Cost

16. TAM Wire Reuse with Fixed Test Architectures Example

17. TAM Wire Reuse with Flexible Pre-bond Test Architecture Change test architecture for pre-bond tests, further reduce their routing cost Sacrifice only limited testing time

18. TAM Wire Reuse with Flexible Pre-bond Test Architecture Outer SA-based Core Assignment Rules Redundancy Two ascending order If i<j, keep the smallest core index assigned to TAM i smaller than that assigned to TAM j Prove of completeness

19. TAM Wire Reuse with Flexible Pre-bond Test Architecture Inner TAM Width Allocation Procedure Short running time Greedy Heuristic Close-to-optimal Solution 4 4. S. K. Goel and E. J. Marinissen. Effective and Efficient Test Architecture Design for SOCs. In Proceedings IEEE International Test Conference (ITC), pages 529–538, Baltimore, MD, Oct. 2002.

20. Outline Introduction Motivation Approach Experiments Conclusion

21. Experiments Results Width (bit) Routing Fix Time Compensate Routing Flexible Routing Fix Time Compensate Routing Flexible 16 P22810P22810 -14.70%1.16%-32.30% P93791P93791 -8.50%2.63%-47.34% 24-9.23%1.09%-25.50%-12.41%0.30%-43.55% 32-10.60%0.93%-36.90%-7.29%1.86%-49.39% 40-18.70%0.48%-43.40%-9.07%2.58%-44.54% 48-8.34%0.50%-24.90%-13.36%0.71%-47.76% 56-8.16%0.23%-37.30%-12.34%1.53%-46.23% 64-6.20%0.54%-35.80%-10.81%1.71%-48.80%

22. Experiments Results Width (bit) Routing Fix Time Compensate Routing Flexible Routing Fix Time Compensa te Routing Flexible 16 P34392P34392 -10.29%-0.54%-48.79% T512505T512505 -10.55%0%-26.70% 24-17.59%-0.62%-36.93%-10.57%0.33%-26.76% 32-16.95%0.16%-44.69%-16.37%0.43%-41.73% 40-21.23%-2.55%-43.67%-11.61%1.35%-26.42% 48-15.16%-0.33%-29.33%-11.61%0.88%-26.42% 56-12.91%15.77%-31.25%-11.61%0.43%-26.42% 64-12.91%11.86%-32.06%-11.61%1.59%-26.42%

23. Experiments Results

24. Outline Introduction Motivation Approach Experiments Conclusion

25. Only fabricate a limited number of test pads for pre-bond testing Dedicated pre-bond and post-bond test architectures to satisfy the given test pad constraint Novel layout-driven optimization techniques to share the TAM routing resources between pre- bond tests and post-bond test

26. Thank You Q & A