1. PIC Processor Design CPE 428/528 April 29, 2002 Dr. Milenkovic Presented by: David Fatzer Le Pitts William Cruger Donn Hall

2. Introduction Project Description – Build a Soft Core for a PIC18 Series Microcontroller Motivation – Desire to Gain Further Understanding of Microprocessor Architecture – Apply VHDL Techniques to a Real-World Situation

3. Platform FPGA – Spartan II – 600 Complex Logic Blocks (20x30) – 100,000 Gates – 10 Configurable 4K bit block RAMs – Dedicated carry logic for high-speed arithmetic

4. Spartan II Demo Board 2-Digit LCD RS-232 Port User LED’s User Switches 2.5 and 3.3 Volt Regulators JTAG Port Oscillator, 30MHz – 50MHz

5. Demo Board Modifications 3.6864 MHz Oscillator LCD Module Display 4 Lines x 20 Characters 5V Power Source for LCD

6. Development Tools Model Technology – ModelSim – VHDL Composition – Pre-Synthesis Testing Xilinx ISE WebPack – VHDL Synthesis – VHDL Implementation MicroChip MPLAB Assembler – ROM test code

7. PIC Description Microcontrol Unit 16-bit Wide Instruction Width 8-bit Wide Data Bus Two-Stage Pipeline Single Cycle Execution versus Microchip’s Four Cycle Execution

8. PIC Components ROM Register File Data Processing Unit Instruction Fetch Unit Instruction Decode Unit Reset Controller Input/Output Latches

9. ROM Provides Storage – OP-Codes – Data Constants – Strings for Test and Application Code Includes 256 x 16-bit Words Utilizes On-Chip Block RAM

10. Register File Provides the Following – Storage and Decoding for One Bank of a 128 8-bit General Purpose Register – Decoding for Special Function Registers – Five Condition Code Registers Utilizes 4096-bit on Chip Block RAM

11. Data Processing Unit (DPU) Handles all Data Processing Functions Components – Arithmetic Logic Unit (ALU) – Multiplier – Rotate Unit (RU) – Bit Operation Unit (BOU) – Working Register (WREG/Accumulator)

12. Data Processing Unit (DPU) Register File Rotator Unit Multiplier MuxAMuxB ALU Bit Unit WREG Literal Bus FileWriteBus FileReadBus WRegBus

13. DPU – Arithmetic Logic Unit Two 8-bit Inputs One 8-bit Output Four Operations - AND, OR, XOR, ADD Pre-Conditioners – PASS – Do Nothing to the Input – INVERT – Invert the Input – Force0 – Force the Input to all Zeroes – Force1 – Force the Input to all Ones Generates Condition Codes

14. DPU – Arithmetic Logic Unit

15. ALU Condition Codes Condition CodeImplementation Negative1 when AluResult(7) = 1 Zero1 when AluResult(7..0) = all 0s Carry1 when AluCarry(7) = 1 Overflow1 when AluCarry(7) != AluCarry(6) DigitCarryNot yet implemented

16. DPU – Multiplier Single Cycle Using Combinatorial Array Multiplier Two 8-bit Unsigned Inputs One 16-bit Unsigned Output Stored in Two 8-bit Special Function Registers

17. DPU – Rotate Unit Performs Single Position Rotate and Nibble Swapping Combinatorial Implementation

18. DPU – Rotate Unit Rotate Unit Operations RotateUnitFunctionCodeEffect on Stack Pointer RLCFRotate Left through Carry RLNCFRotate Left RRCFRotate Right through Carry RRNCFRotate Right SWAPSwap Nibbles

19. DPU – Bit Operation Unit Provides Mask for Bit-Oriented Operations Bit Operation Decoding Instruction Word Bits[11..9]Bit Operation Unit Output Bits[7..0] 00000000001 00100000010 01000000100 01100001000 10000010000 10100100000 11001000000 11110000000

20. DPU – Working Register Provides a Temporary Storage Register That Serves as an Accumulator For All Data Processing instructions, Bit 9 Determines whether the Result of the Operation is Stored in Working Register or the Register File

21. Instruction Fetch Unit (IFU) Updates Program Counter Manages Hardware Return Stack Updates Instruction Register Manages Table Pointer

22. IFU – Block Diagram

23. IFU – Program Counter 21-bits (2MB Address Space) Asynchronous Reset Updated on Rising Edge of Clock ProgramCounterOpcode Determines Function

24. IFU – Program Counter Program Counter Opcodes ProgramCounterOpcodeEffect on PC NextInstructionIncrement to next address (+1) BranchRelativeOffset8Add 8-bit signed offset (-127 to +128) BranchRelativeOffset11Add 11-bit signed offset (-1024 to +1023) BranchAbsoluteForce new 21-bit value (GOTO) RestoreFromTopOfStackUse top of return stack value (RETURN) DontFetchDo not change (+0) InterruptHighPriorityForce to high priority interrupt vector (address 8) InterruptLowPriorityForce to low priority interrupt vector (address 18)

25. IFU – Return Stack 21-bit Wide by 16 Deep Stores Return Addresses Implemented Using Block RAM

26. IFU – Return Stack Stack Pointer Operations StackOpcodeEffect on Stack Pointer StackNOPDo not change (+0) StackPUSHAdd 1 then store (pre-increment) StackPOPRetreive then subtract 1 (post-decrement)

27. IFU – Instruction Register Latches Instructions from Program Data Bus Two-Stage Pipeline – Fetch Next Instruction – Decode & Execute Current Instruction

28. IFU – Instruction Register Instruction Register Operations InstructionRegisterOpcodeEffect on Instruction Register LatchNextInstructionLatch new instruction ForceNOPForce instruction register to all 0’s (NOP)

29. IFU – Table Pointer Instruction Facilitates Movement of Data to and from the ROM 21-bits Wide to Address 2MB of ROM Table Latch Register – Bridge for Program and Data Buses

30. IFU – Table Pointer Instruction Table Address Assignments Instruction Register(1:0) Operation on Table Pointer Next Value Table Address 00No changeTable Pointer 01Post-IncrementTable Pointer + 1Table Pointer 10Post-DecrementTable Pointer - 1Table Pointer 11Pre-IncrementTable Pointer + 1Table Pointer Next Value

31. IFU – Table Pointer Instruction Table Function Op-Codes TableFunctionOpCodeOperation on Table Latch (TABLAT) TableFunctionNOPNo change TableFunctionReadContents of TableAddress are written to TABLAT TableFunctionWriteContents of TABLAT written to ROM at TableAddress

32. IFU – Table Pointer Instruction Key Signals – Program Address Address Bus to ROM Normally Follows Program Counter Follows Table Address For Table Pointer Instructions – Program Data Data Bus From the ROM High-Impedance Except on TableFunctionWrite –TableFunctionWrite Used to Program Flash

33. Instruction Decoder - ID Three Distinct Stages of Design – Instruction Disassembler Identifies Instruction from Opcode – Define Global Decode Signals – Assign Global Decode Signals Must Include all Global Signals in Each Instruction to Avoid Latches

34. ID – Instruction Disassembler Instruction Decoder Grouping Group # Instruction Bits(15..12) Assembly Instruction 0000NOP, MOVLB, RESET, RETFIE, RETURN, CLRWDT, DAW, POP, PUSH, SLEEP, TBLRD, TBLWT, DECF, SUBLW, IORLW, XORLW, ANDLW, RETLW, MULLW, MOVLW, ADDLW 0001IORWF, ANDWF, XORWF, COMF 0010ADDWF, ADDWFC, DECFSZ, INCF 0011INCFSZ, RLCF, RRCF, SWAPF 0100DCFSNZ, INFSNZ, RLNCF, RRNCF 0101SUBFWB, SUBFW, SUBWFB, MOVF 0110CPFSEG, CPFSGT, CPFSLT, CLRF, SETF, MOVWF, NEGF, TSTFSZ 0111BTG 1000BSF 1001BCF 1010BTFSS 1011BTFSC 1100MOVFF 1101BRA, RCALL 1110BC, BN, BNC, BNN, BNOV, BNC, BOV, BZ, GOTO, CALL, LFSR 1111NOP (Second half of two-word instruction)

35. ID – Global Decode Signals Signal NameSignal Function MuxASelectSelects either register file or literal value for ALU input A MuxBSelectSelects either W-Register or Bit-Op value for ALU input B RotateUnitEnableEnables Rotate Unit RotateUnitFunctionCodeSelects RU function (Rotate Left, Right, with/without carry) ALUEnableEnables ALU ALUFunctionCodeALU function code (AND, OR, XOR ADD) ALUBusACondCodeALU input a conditioner (Pass, Invert, Force0s, Force1s) ALUBusBCondCodeALU input B conditioner (Pass, Invert, Force0s, Force1s) ALUCarryCondCodeALU carry input conditioner (Pass, Invert, Force0, Force1) BitOpEnableEnables Bit-Op unit BitOpPositionSelects Bit-OP position ( 1,2,4,8,16,32,64,128 ) UpdateConditionCodesSet to 1 to enable change in corresponding condition code WRegWriteEnableEnables writes from WriteBus to WREG on next rising edge FileWriteEnableEnables writes from WriteBus to Register File on next rising edge ProgramCounterOpCodeTells how to prepare Program Counter for next cycle InstructionRegisterOpcodeTells how to prepare Instruction Register for next cycle StackOpCodeStack function code. (Push, Pop, Nop) MultiplierEnableEnables single-cycle combinatorial multiplier ClearWatchdogTimerSet to 1 by CLRWDT instruction to clear watchdog timer SoftwareResetSet by RESET instruction to reset unit BSRWriteEnableSet to enable updates to Bank Select Register DAWEnableEnables Decimal Adjust Accumulator Unit TableFunctionOpCodeTable-pointer function code. (Read, Write, NOP) SleepModeSet by SLEEP instruction to freeze clock until next external reset

36. Reset Controller - RC Provides Global Reset Signal to PIC Reset Sources – External Reset – Software Reset – Stack Error – Watchdog Timeout Watchdog Timer Module

37. RC - Watchdog Timer Module 17-Stage Ripple Counter 36ms Timeout Based On 3.6864 MHz Asynchronous Clear – Reset – Clear from CLRWDT Instruction

38. Input/Output Latches Provides Three 8-bit Bi-Directional Ports for Parallel Communications Two of the Three Ports are for Communication with the LCD Module

39. Implementation Results

40. Device Utilization - 74% Clock Cycle – 21.125MHz – Multiplier Determines Critical Datapath

41. Design Process Assembly Program Assembler Converter (.HEX to ASCII) Load ROM (Copy/Paste)ModelSim Simulation/Verification VHDL Model Synthesis

42. Future Consideration Core for Future System-On-Chip Designs Further Exhaustive Testing External Flash Memory Implementation High-Level Language Applications ASIC Synthesis

43. Questions?