1. BITWISE OPERATIONS 353156 – Microprocessor Asst. Prof. Dr. Choopan Rattanapoka and Asst. Prof. Dr. Suphot Chunwiphat

2. Objectives  To understand  Bitwise Logical Operations OR AND XOR  Shift Operations Shift Left Shift Right Rotate

3. Bitwise Operations (1)  Up until now, we’ve done :  Arithmetic (ADD, SUB, RSB,..etc..)  Some of data movement (MOV)  All of these instructions view content of register as a single quantity  But for bitwise operations, we will see the content of register as 32 bits rather than as a single 32-bit number

4. Bitwise Operations (2)  Since register are composed of 32 bits, we may want to access individual bits rather than the whole.  Introduction two new classes of instructions/operations :  Logical Instruction  Shift Operations

5. Logical Operations  Operator Names:  AND  BIC  ORR  EOR  Operands  Destination : Register  Operand1 : Register  Operand2 : Register, Shifted Register, Immediate  Example  AND a1, v1, v2  AND a1, v1, #0x40

6. Logical AND Operator  AND (truth table)  AND : bit-by-bit operation leaves a 1 in the result only if both bits of the operands are 1 ABA AND B 000 010 100 111

7. Example : Logical AND Operator  Assume that register A and B are 8-bit register  Let A stores value 0011 1011  Let B stores value 1001 0010  Find A AND B 0 0 1 1 1 0 1 1 AND 1 0 0 1 0 0 1 0 01000001

8. Exercise 1: Logical AND Operator  What is the value store in register R0 after the execution of program is done AREA ex1_1, CODE, READONLY ENTRY start MOV a2, #0x42 MOV a3, #0xFC AND a1, a2, a3 END AREA ex1_2, CODE, READONLY ENTRY start MOV a2, #0xBC000000 AND a1, a2, #0xFF END (1)(2)

9. Logical BIC (AND NOT) Operator  BIC (BIt Clean) : bit-by-bit operation leaves a 1 in the result only if bit of the first operand is 1 and the second operands 0  Example 0011BIC 0101 0100

10. Exercise 2: Logical BIC Operator  What is the value store in register R0 after the execution of program is done AREA ex2_1, CODE, READONLY ENTRY start MOV a2, #0x42 MOV a3, #0xFC BIC a1, a2, a3 END AREA ex2_2, CODE, READONLY ENTRY start MOV a2, #0xBC000000 BIC a1, a2, #0xFF END (1)(2)

11. MASK  AND and BIC normally use to create a mask  Example : Given R0 stores 0x12345678  if we want to keep only the value of the last 2 bytes and we want to clear the first 2 bytes to 0 (0x00005678) R1 stores 0xFFFF AND R0, R0, R1 ; short written constant value  if we want to keep only the value of the first 2 bytes and we want to clear the last 2 bytes to 0 (0x12340000) R1 stores 0xFFFF0000 AND R0, R0, R1 ; long written constant value R2 stores 0xFFFF BIC R0, R0, R2 ; better ?

12. Logical OR Operator  OR (truth table)  OR : bit-by-bit operation leaves a 1 in the result if either bit of the operands is 1 ABA OR B 000 011 101 111

13. Example : Logical OR Operator  Assume that register A and B are 8-bit register  Let A = 0011 1011, and B = 1001 0010  Find A OR B 0 0 1 1 1 0 1 1 OR 1 0 0 1 0 0 1 0  Example : ARM Instruction  ORRR0, R0, #0x20 11011011

14. Exercise 3 : Logical OR Operator  What is the value store in register R0 after the execution of program is done AREA ex3_1, CODE, READONLY ENTRY start MOV a2, #0x34 MOV a3, #0x86 ORR a1, a2, a3 END

15. Logical XOR Operator  XOR (truth table)  XOR : bit-by-bit operation leaves a 1 in the result if bit of the operands are different ABA XOR B 000 011 101 110

16. Example : Logical XOR Operator  Assume that register A and B are 8-bit register  Let A = 0011 1011, and B = 1001 0010  Find A XOR B 0 0 1 1 1 0 1 1 XOR 1 0 0 1 0 0 1 0  Example : ARM Instruction  EORR0, R0, #0x20 10011010

17. Exercise 4 : Logical XOR Operator  What is the value store in register R0 after the execution of program is done AREA ex4_1, CODE, READONLY ENTRY start MOV a2, #0x34 MOV a3, #0x86 EOR a1, a2, a3 END

18. Shift Operations  Shift means move all the bits in a word to the left or right by number of bits  In ARM, there are 3 types of shift operations  Fill emptied bits with 0s (LSL, LSR)  Fill emptied bits with sign bits (ASR)  Fill emptied bits with the bits falling (rotation) (ROR)

19. Shift Operations (Type 1)  Move all the bits in a word to the left or right by a number of bits, filling the emptied bits with 0s  Example : Given A an 8-bit register which stores data 1100 1010 11001010 110101000000 Shift right by 4 bits Shift left by 4 bits 010110000001

20. LSL, LSR Instructions  In ARM, we have 2 instructions for shift operation type 1  LSL (Logical Shift Left)  LSR (Logical Shift Right)  We can use 2 formats of instruction  Opcode dest_reg, reg_contains_number_of_bit_to_shift LSL R0, R1 ; R1 must store number of bit to shift  Opcode dest_reg, src_reg, constant_number_of_bit_to_shift LSR R0, R1, #4 ; Shift right value in R1 for 4 bits and then store it to R0  ** Only R0-R7 can do Shift operations **

21. Exercise 5: LSL, LSR Operations  What is the value store in register R0 after the execution of program is done AREA ex5_1, CODE, READONLY ENTRY start MOV a1, #0x01 MOV a2, #4 LSL a1, a2 END AREA ex5_2, CODE, READONLY ENTRY start MOV a1, #0xFF LSR a1, a1, #0x4 END (1)(2)

22. Shift Operations (Type 2)  Move all the bits in a word to the right by a number of bits, filling the emptied bits with sign bits  Example :  Given A an 8-bit register which stores data 1100 1010  Given A an 8-bit register which stores data 0100 1010 11001010 110101001111 Shift right by 4 bits 01001010 110101000000

23. ASR Instructions  ASR (Arithmatic Shift Right)  We can use 2 formats of instruction  Opcode dest_reg, reg_contains_number_of_bit_to_shift ASR R0, R1 ; R1 must store number of bit to shift  Opcode dest_reg, src_reg, constant_number_of_bit_to_shift ASR R0, R1, #4 ; Shift right value in R1 for 4 bits and then store it to R0  ** Only R0-R7 can do Shift operations **

24. Exercise 6: ASR Operations  What is the value store in register R0 after the execution of program is done AREA ex6_1, CODE, READONLY ENTRY start MOV a1, #0xFFFFFF10 MOV a2, #2 ASR a1, a2 END AREA ex6_2, CODE, READONLY ENTRY start MOV a1, #0xFF ASR a1, a1, #0x2 END (1)(2)

25. Shift Operations (Type 3)  Move all the bits in a word to the right by a number of bits, filling the emptied bits with the bits falling of the right  Example : Given A an 8-bit register which stores data 1100 1010 Rotate right by 3 bits 11001010 0 00101110 1 00101011 0

26. ROR Instructions  ROR (ROtate Right)  We can use 2 formats of instruction  Opcode dest_reg, reg_contains_number_of_bit_to_shift ROR R0, R1 ; R1 must store number of bit to shift  Opcode dest_reg, src_reg, constant_number_of_bit_to_shift ROR R0, R1, #4 ; Rorate right value in R1 for 4 bits and then store it to R0  ** Only R0-R7 can do Shift operations **

27. Exercise 7: ROR Operations  What is the value store in register R0 after the execution of program is done AREA ex7_1, CODE, READONLY ENTRY start MOV a1, #0xFFFFFF10 MOV a2, #4 ROR a1, a2 END AREA ex7_2, CODE, READONLY ENTRY start MOV a1, #0xFF ROR a1, a1, #0x4 END (1)(2)

28. Review : 2 nd Operand  2 nd operand for operation :  register  immediate (numerical constant)  shifted register  Example :  MOV R0, R1  MOV R0, #0x12  MOV R0, R1, LSL #4 ; R0  (R1 << 4)

29. Barrel Shifter : The Second Operand  Register, optionally with shift operation applied  Shift value can be either :  5 bit unsigned integer ADD R0, R1, R2, LSL #8 ;R0  R1 + (R2 << 8 bits)  Specified in bottom of another register ADD R0, R1, R2, LSL R3 ;R0  R1 + (R2 << R3 bits) ALU Barrel Shifter Operand 1Operand 2 Result  Immediate value  8 bit number  Can be rotated right through as even number of position  Assembler will calculate rotate for you from constant ADD R0, R1, #10 ; R0  R1 + 10 ADD R0, R1, #0xFF00 ; R0  R1 + (0xFF << 16 bits) ADD R0, R1, #0xFFF ; ERROR

30. Assignment 5  What is the value store in register R0 after the execution of program is done (explain the result of each instruction) AREA hw5_1, CODE, READONLY ENTRY start MOV a1, #0xFFFFFF18 MOV a2, #16 ROR a1, a2 MOV a2, #0xFF000000 AND a1, a1, a2, LSR #4 LSR a1, #16 END AREA hw5_2, CODE, READONLY ENTRY start MOV a1, #0xFF MOV a2, #0xCC MOV a3, #16 ADD a1, a1, a2, LSL a3 EOR a2, a2, #0x65 ORR a1, a1, a2, LSL #8 END (1) (2)