1. Logic Gates Logic gates are electronic digital circuit perform logic functions. Commonly expected logic functions are already having the corresponding logic circuits in Integrated Circuit (I.C.) form.

2. Design of Circuit Procedures 1. Obtain a precise circuit specification Obtain a precise circuit specification 2. Development of a truth table Development of a truth table 3. Identifying the minterms corresponding to each row in the table. Identifying the minterms corresponding to each row in the table. 4. Drawing Karnaugh maps Drawing Karnaugh maps 5. Forming groups of 1's on the Karnough map Forming groups of 1's on the Karnough map 6. Writing the reduced expression Writing the reduced expression 7. Converting the reduced expression into a realizable expression Converting the reduced expression into a realizable expression 8. Drawing the circuit diagram Drawing the circuit diagram 9. Construct and test a prototype circuit. Construct and test a prototype circuit.

3. Types of Logic Gates

4. Basic Gates AND, OR, NOT

5. AND Gate The AND gate implements the Boolean AND function where the output only is logical 1 when all inputs are logical 1. The standard symbol and the truth tabel for a two input AND gate is:

6. Boolean expression of AND The Boolean expression for the AND gate is R=A.B ABR 000 010 100 111

7. OR Gate The OR gate implements the Boolean OR function where the output is logical 1 when just input is logical 1. The standard symbol and the truth table for a two input OR gate is:

8. Boolean Expression of OR ABR 000 011 101 111 The Boolean expression for the OR gate is: R=A+B

9. NOT Gate The NOT gate implements the Boolean NOT function where the output is the inverse of the input. The standard symbol and the truth table for the NOT gate is:

10. Boolean Expression of NOT The Boolean expression for the NOT gate is: R=-A AR 01 00

11. Derived Gates NAND, NOR, XOR

12. NAND Gate The NAND gate is an AND gate followed by a NOT gate. The output is logical 1 when one of the inputs are logical 0 The standard symbol and the truth table for the NAND gate is:

13. Boolean expression of NAND ABR 001 011 101 110

14. NOR Gate The NOR is a combination of an OR followed by a NOT gate. The output is logical 1 when non of the inputs are logical 0 The standard symbol and the truth table for the NOR gate is:

15. Boolean Expression of NOR ABR 001 010 100 110

16. XOR Gate The XOR gate produces a logic 1 output only if its two inputs are different. If the inputs are the same, the output is a logic 0 The XOR symbol is a variation on the standard OR symbol. It consists of a plus (+) sign with a circle around it. The logic symbol, as shown here, is a variation on the standard OR symbol.

17. Exercise 1 http://kom.auc.dk/logic/

18. De-Morgan ’ s Theorem and Logic Conversion 1) 2) 3) 4)

19. Implement the logic expression using NAND gates only 1) 2)

20. Implement logic expression using NOR gates only 1)

21. Revision Exercise http://www.nottingham.ac.uk/~cczwoo d/TestCourses/logic/logic-intro.html http://www.nottingham.ac.uk/~cczwoo d/TestCourses/logic/logic-intro.html http://www.cs.odu.edu/~jbollen/CS149 /demos.html http://www.cs.odu.edu/~jbollen/CS149 /demos.html http://sandbox.mc.edu/~bennet/cs110/ boolalg/gate.html http://sandbox.mc.edu/~bennet/cs110/ boolalg/gate.html http://www.cs.stedwards.edu/~jsnowd e/start.htm http://www.cs.stedwards.edu/~jsnowd e/start.htm

22. Combinational Logic Designs A combinational logic circuit can be described by the block schematic shown Each output is a function of some or all of the input variables, Hence O 1 =f(I 1,I 2,....,I n ) O 2 =f(I 1,I 2, …,I n )... andO n =f(I 1,I 2, …,I n ) :::: :::: Combinational Logic I1I1 InIn O1O1 OnOn

23. Half Adder

24. What is a Half adder? Logic gate that perform addition for 1- bit When 1 + 1 occurs, a carry produce 1

25. Half Adder Perform arithmetic additions two inputs A, B to half-adder. Resultants are Sum(S) and Carry(C out ) Using K-Map to simplify the sum term, we get H.A A BC out S

26. Full Adder

27. What is Full Adder? A full adder is a circuit that computes the sum of three bits and gives a two-bit answer. A circuit for adding two 16-bit numbers can be built from 16 full-adder circuits. Each full- adder does one column of the sum. The full adder for a given column adds two bits from the input numbers together with a one-bit carry from the previous column to the right. The adder produces a two-bit answer; one of these bits is used as a carry into the next column.

28. Full Adder A full adder has 3 inputs and 2 outputs The truth table of the full-adder can be drawn with inputs A,B and Cin with outputs S and Cout From the truth table we can write the Boolean equation for the S and Cout Simplify using Boolean Algebra and K-map, we get

29. Sum = Any 2 of the three inputs are 1 Cout = XOR between A, B, Cin ABCinSumCout 00000 00101 01001 01110 10001 10110 11010 11111

30. Full Adder diagram

31. Half Subtractor

32. What is a Half Subtractor A logic gate that perform 1 bit subtraction When 0-1 occurs, a carry produces 1

33. Half Subtractor CABD 0001 0 0 0 1 1 1 1 0 1 1 0 0 A 0 B 0 D 0 C 1 0 1 2 1

34. Half Subtractor Operation: A - B

35. Full Subtractor

36. What is a Full Subtraction? Logic gates that perform two bits subtraction

37. Full Subtractor 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 C i A i B i D i C i+1 11 11 CiCi AiBiAiBi 00011110 0 1 DiDi D i = C i $ (A i $ B i ) Same as S i in full adder

38. Full Subtractor 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 C i A i B i D i C i+1 CiCi AiBiAiBi 00011110 0 1 1 111 C i+1 C i+1 = !A i & B i # C i & !A i & !B i # C i & A i & B i

39. Full Subtractor C i+1 = !A i & B i # C i & !A i & !B i # C i & A i & B i C i+1 = !A i & B i # C i & (!A i & !B i # A i & B i ) C i+1 = !A i & B i # C i & !(A i $ B i ) Recall: D i = C i $ (A i $ B i ) C i+1 = !A i & B i # C i & !(A i $ B i )

40. Full Subtractor D i = C i $ (A i $ B i ) C i+1 = !A i & B i # C i & !(A i $ B i ) half subtractor

41. Full Subtractor Operation: A - B - B in

42. Adder/Subtractor - 1 A 0 B 0 D 0 C 1 A 0 B 0 S 0 C 1 Half adder Half subtractor E = 0: Half adder E = 1: Half subtractor

43. Adder/Subtractor-1 i+1 E = 0: Full adder E = 1: Full subtractor

44. 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 C i A i B i S i C i+1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 C i A i B i S i C i+1 Full Adder Reordered Full Adder 0 0 0 0 0 0 0 1 1 1 0 1 0 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 1 1 1 1 C i A i B i D i C i+1 Full Subtractor NOT

45. Making a full subtractor from a full adder

46. Four-Bit Parallel Adder This circuit is sometimes referred to as a ripple- through adder C0 ripples through four two-level logic circuits and hence the sum cannot be completed until eight gate delays For this kind of adder, the maximum delay is directly proportional to the number of stages n.

47. Adder/Subtractor-2 E = 0: 4-bit adder E = 1: 4-bit subtractor

48. Carry Look-Ahead Circuit To improve the speed of addition Consider the carry output equation for a full adder is Which can be expressed as follows or as where

49. Carry Look-Ahead Circuit Four a four-bit adder the generate and propagate terms for each stage are while the carries for the various stages are

50. Carry Look-Ahead Circuit Substituting for C 0 in the C 1 equation etc leads to the following equations: And the sum Since the number of levels of logic required when a large number of bits has to be added does not increase then the Carry Look-Ahead adder will provide a faster addition time

51. Binary Multiplication Paper and Pen method which is implemented using 9 AND gates, 3 FA and 3 HA