1. MCS51 - lecture 4

2. Lecture 3 1/27 Serial ports MCS51 Standard SIO Some extensions and modifications

3. MCS51 - standard SIO 2/27 Standard SIO features: possible half-duplex 8-bit data synchronous communication at constant speed; possible full-duplex 8- or 9-bit data asynchronous communication at constant or programmable speed; communication with shorter data words (5, 6, 7 bits) - only with special software single buffer for receiver and transmitter; data accessible through buffer register SBUF; controlled by register SCON & bit SMOD in reg. PCON; possible multiprocessor communication; end of receiving and transmitting signalling by flags RI & TI; interrupt request as logical RI or TI.

4. MCS51 - standard SIO 3/27 Control register: SM0,SM1,SM2 - working mode selection: 0 0 0 - mode 0 - synchronous 0 1 0 - mode 1 - asynchronous 0 1 1 - mode 1 - asynchronous with waiting for correct stop bit 1 0 0 - mode 2 - asynchronous 1 0 1 - mode 2 - asynchronous with ignoring received data, which 9th bit is cleared 1 1 0 - mode 3 - asynchronous 1 1 1 - mode 3 - asynchronous with ignoring received data, which 9th bit is cleared SM0 9F SM1 9E SM2 9D REN 9C TB8 9B RB8 9A TI 99 RI 98 SCON98h

5. MCS51 - standard SIO 4/27 REN - receiver enabling bit TB8 - 9th data bit to send (in mode 2 & 3) RB8 - received 9th data bit (in mode 2 & 3) TI - transmitter interrupt flag, set after sending last bit, should be cleared by software RI - receiver interrupt flag, set after receiving last bit, should be cleared by software SMOD---GF1GF0PDIDL PCON87h 99hSBUF SMOD - double speed bit of SIO port in mode 1,2 i 3 SBUF - buffer data register

6. MCS51 - standard SIO 5/27 Mode 0 - synchronous

7. Mode 0 communication MCS51 - standard SIO 6/27

8. MCS51 - standard SIO 7/27 Mode 1 - 8-bit, asynchronous

9. MCS51 - standard SIO 8/27 Mode 1 - communication

10. MCS51 - standard SIO 9/27 Mode 2 & 3 - 9-bit, asynchronous

11. MCS51 - standard SIO 10/27 Mode 2 & 3 - communication

12. MCS51 - standard SIO 11/27 Possible baud rates: 1. synchronous mode: f B = f CLK /12 2. asynchronous mode 1 & 3: f B = 2 SMOD  f TF1 /32 3. asynchronous mode 2: f B = 2 SMOD  f CLK /64 Using timer/counter 1 with 8-bit automatic reload: f B = 2 SMOD  f CLK : 12 : 32 : (256-TH1) Using timer/counter 2 with 16-bit reload: f B = f CLK : 32 : (65536-RCAP2)

13. MCS51 - standard SIO 12/27

14. MCS51 - standard SIO 13/27 Baud rate ( f B ) tuning during receiving: Receiving with match frequencies f B = f B * : Receiving with f B > f B * : Receiving with f B < f B * : receive start (falling edge) clearing divider ‘:16’ new synchronization No-error condition: correct read last data bit (RB8) & STOP_bit=1

15. MCS51 - standard SIO 14/27 0 1 2 3 4 5 6 7 8 9 A B C D E F divider ‘:16’ content during bit detection in mode 1,2 i 3 RxD input 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B C D STOP (11 bit of frame) (10+6/16)1/f BMAX (10+10/16)1/f BMIN 10  1/f B * 11  1/f B *

16. MCS51 - standard SIO 15/27 Receiver frequency f B tolerance estimation:

17. MCS51 - standard SIO 16/27 Baud rate ( f B ) tuning during transmitting Transmitting with match frequencies z f B = f B * : Transmitting with higher f B > f B * : Transmitting with lower f B < f B * : transmitting start new synchronization No-error transmit/receive condition: correct read last data bit (RB8) & STOP_bit=1

18. MCS51 - standard SIO 17/27 0 1 2 3 4 5 6 7 8 9 A B C D E F divider ‘:16’ content during bit detection in mode 1,2 i 3 RxD input 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A B STOP (11 bit of frame) 11  1/f BMAX 10  1/f BMIN (10+6/16)  1/f B * (10+10/16)  1/f B *

19. MCS51 - standard SIO 18/27 Transmitter frequency f B tolerance estimation : Receiver tolerance range is less, so it becomes obligatory:

20. MCS51 - standard SIO 19/27 Possibilities of achieving correct baud rates f B  on different f CLK

21. MCS51 - standard SIO 20/27 Multiprocessor communication RxD TxD  C1 RxD TxD  C2 RxD TxD  Ck distributed system data exchange; processes synchronization; data acquisition...

22. MCS51 - standard SIO 21/27 SIO port in multiprocessor communication: connect terminal RxD & TxD to single transmission line; utilize mode 2 & 3 with bit SM2=1 - it allows to receive only frames with set 9th bit (RB8); only one microcontroller can be superior; superior microcontroller has cleared bit SM2; subordinate microcontrollers should have bit SM2=1; each microcontroller should have individual 8-bit address; “common address” can be used for broadcasting; in SIO interrupt service routine, if RI=1 at the first calling address should be checked.

23. MCS51 - standard SIO 22/27 Exemplary algorithm: 1. Superior processor send the frame with calling (or common) address and set TB8 bit - address describes destination for following data. 2. All other processor, acting as subordinate, have set SM2 bit and will receive this calling frame - calling address will be placed in SBUF and flag RI is set. 3. SIO service routine starts in each microcontroller and according to state: RI=1 & SM2=1 compares content of SBUF with local or common address. 4. If any processor recognize the address, it clear his SM2 bit and finishes service routine, other processors finish their SIO service with SM2=1. 5. Data exchange between superior processor and addressed subordinate one starts at SM2=0 & cleared TB8/RB8 bits. SIO of other processors ignore such data frame. 6. At the end of communication subordinate processor sets SM2=1.

24. MCS51 - extended SIO 23/27 Additional functions: 1. STOP bit error detection - the absence ‘1’ at expected moment - so called frame error, additional bit FE, which can be checked by reading SM0 bit from SCON. 2. Automatic calling address matching during multiprocessor communication - enabled by SM2=1; 3. In mode 1 all received bytes with correct STOP bit are analysed, and in mode 2 & 3 - only these with RB8=1.

25. MCS51 - extended SIO 24/27 RI flag is set only if received byte matches to programmed address mask. 2 additional SFR registers: SADDR0A9h SADEN0B9h Received address-byte matches with pattern, if : (received_byte  SADDR)  SADEN = 00h Example: in  C1 were set:in  C2 were set: SADDR=1100000111000010 SADEN=1111111011111101 active address=1100000x110000x1 So calling address 11000001 activate only  C1, address 11000010 - only  C2, address 11000000 - both  C, and any address matched with xxxxxx11 will be ignored.

26. MCS51 - additional SIO 25/27 For example Siemens’ microcontroller Functions: only asynchronous communication (modes 1,2 & 3; own baud rate generator; registers like in standard (S1BUF i S1CON)

27. MCS51 - other serial interfaces 26/27 SPI - full-duplex synchronous bus, to communication with specialised peripherals, configuration memories, or to programming ISP. Served by set of registers (SPDR, SPSR, SPCR) I2C - half-duplex synchronous bus, to communication with specialised peripherals, configuration memories. Two variants are met: 1. hardware support at byte level (for example registers S1DAT, S1CON, S1SRA i S1ADR in C552) 2. hardware support at bit level (for example registers: S1INT, S1BIT & S1SCS in C524, or I2CON, I2DAT, I2CFG & I2STA in C751,C752)