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Radix-2 2 Based Low Power Reconfigurable FFT Processor Presented by Cheng-Chien Wu, Master Student of CSIE,CCU 1 Author: Gin-Der Wu and Yi-Ming Liu Department.

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Presentation on theme: "Radix-2 2 Based Low Power Reconfigurable FFT Processor Presented by Cheng-Chien Wu, Master Student of CSIE,CCU 1 Author: Gin-Der Wu and Yi-Ming Liu Department."— Presentation transcript:

1 Radix-2 2 Based Low Power Reconfigurable FFT Processor Presented by Cheng-Chien Wu, Master Student of CSIE,CCU 1 Author: Gin-Der Wu and Yi-Ming Liu Department of Electrical Engineering NCNU Source: IEEE International Symposium on Industrial Electronics(ISIE2009)

2 Outline – Introduction – Discrete Fourier Transform(DCT) – Radix - 4 Fast Fourier Transform(FFT) – Radix - 2 2 FFT – Architecture of Radix - 2 2 – Conclusion 2

3 Outline – Introduction – Discrete Fourier Transform(DCT) – Radix - 4 Fast Fourier Transform(FFT) – Radix - 2 2 FFT – Architecture of Radix - 2 2 – Conclusion 3

4 Introduction 4 Fast Fourier Transform (FFT) is widely applied in the speech processing, image processing, and communication system.

5 Introduction(cont’d) 5 Important FFT issues – High throughput – FFT size – Power consumption

6 Outline – Introduction – Discrete Fourier Transform(DCT) – Radix - 4 Fast Fourier Transform(FFT) – Radix - 2 2 FFT – Architecture of Radix - 2 2 – Conclusion 6

7 Discrete Fourier Transform(DCT) 7 DFT definition equation: – x: Input array – X: Output array – N: FFT size – W: Twiddle Factor – n: Input element – K: Output element NxN adders NxN multipliers

8 DCT(cont’d) 8 Twiddle factor: – e: natural number – X: Output array – N: FFT size – n: Input element – K: Output element – i: Imaginary unit

9 Outline – Introduction – Discrete Fourier Transform(DCT) – Radix - 4 Fast Fourier Transform(FFT) – Radix - 2 2 FFT – Architecture of Radix - 2 2 – Conclusion 9

10 DCT to FFT 10 An FFT computes the DFT and produces exactly the same result as evaluating the DFT definition directly the only difference is that an FFT is much faster

11 Radix-4 FFT 11 Based on the radix-4 algorithm, the DFT of signal is divided into four partitions Where F = 0,1,2,3…..N-1 ; k = 0,1,2,3…..N/4-1

12 Radix-4 FFT(cont’d) 12

13 Radix-4 FFT(cont’d) 13

14 Radix-4 FFT(cont’d) 14

15 Radix-4 FFT(cont’d) 15 According to the above equations, we use the same manner to obtain the other samples as the following equations

16 Radix-4 FFT(cont’d) 16 Butterfly graph of Radix-4 FFT

17 2 Stage Butterfly graph of Radix-4 17

18 Butterfly graph of Radix-2 FFT 18

19 Outline – Introduction – Discrete Fourier Transform(DCT) – Radix - 4 Fast Fourier Transform(FFT) – Radix - 2 2 FFT – Architecture of Radix - 2 2 – Conclusion 19

20 Radix-2 2 FFT 20 We rewrite the previous equation of radix -4 FFT algorithm as follows

21 Radix-2 2 FFT Insert T1,T2,T3,T4 into equation 21

22 Radix-2 2 FFT BF Butterfly graph of the radix-2 2 FFT 22

23 Compared with the radix - 2 and 4 reduce the multiplication complexity of radix - 4 Much faster than the conventional radix -2 FFT 23

24 Outline – Introduction – Discrete Fourier Transform(DCT) – Radix - 4 Fast Fourier Transform(FFT) – Radix - 2 2 FFT – Architecture of Radix - 2 2 – Conclusion 24

25 Hardware architecture Pipeline based – Single delay feedback pipeline (SDF) – Multiple-path delay commutator pipeline (MDC) Memory based 25

26 Hardware architecture Pipeline based – Single delay feedback pipeline (SDF) – Multiple-path delay commutator pipeline (MDC) Memory based 26

27 Reconfigurable FFT Processor 27

28 Input data with the radix-2 2 The inputs and outputs have 4 real part and 4 imaginary part respectively 28

29 radix-2 2 butterfly unit architecture 29

30 Reconfigurable FFT Processor 30

31 FFT Register array 31

32 Bank 32

33 Analysis The total gate count of the FFT processor is about 195727 synthesized and estimated with TSMC.13 μm standard. The max clock frequency is 100 MHz. The total execution needs 332 clock cycles. The latency is about 3.32μs(332X10ns) 33

34 Power Consumption The main source of power consumption in a typical CMOS logic gate is due to the switching power, Psw. 34

35 Power Consumption(cont’d) Vdd : supply voltage F : clock frequency C load : load capacitance of the gate K : the average number of times that the gate makes an active transition in a single clock cycle. 35

36 Comparison of Several Researches 36

37 Outline – Introduction – Discrete Fourier Transform(DCT) – Radix - 4 Fast Fourier Transform(FFT) – Radix - 2 2 FFT – Architecture of Radix - 2 2 – Conclusion 37

38 Conclusions The Radix - 2 2 FFT processor is low power consumption. The Radix - 2 2 FFT processor has more flexibility. 38

39 Thanks for Listening 39


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