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Nanotechnology on our Desktops Hard Disk Sensor Medium Transistor Gate SourceDrain Switching layer 5 nm Magnetic grain 10 nm Gate oxide 4 nm Well 6 nm.

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Presentation on theme: "Nanotechnology on our Desktops Hard Disk Sensor Medium Transistor Gate SourceDrain Switching layer 5 nm Magnetic grain 10 nm Gate oxide 4 nm Well 6 nm."— Presentation transcript:

1 Nanotechnology on our Desktops Hard Disk Sensor Medium Transistor Gate SourceDrain Switching layer 5 nm Magnetic grain 10 nm Gate oxide 4 nm Well 6 nm

2 Alferov Kroemer Nobel Prize in Physics 2000 Electrons in the Conduction Band Holes in the Valence Band n-type p-type Benefits of a quantum well: 1)Trap electrons and holes in the same quantum well and thereby keep them together longer. 2)Electrons and holes have well-defined, quantized energies, such that most of them contribute to the same laser line.

3 6 nm : Optimum Thickness Quantum Well Laser Optimization

4 The electron flow from source to drain is controlled by the gate voltage. Electrons MOS = Metal-Oxide-Semiconductor FET = Field Effect Transistor The (MOSFET) Transistor

5 TransistorDRAM (Dynamic Random Access Memory) Transistor + Capacitor

6 Moore’s Law of Silicon Electronics The performance of silicon devices increases exponentially. Corollaries: The storage density doubles every 2 years, linear dimensions x ½ every 4 years. The cost per megabyte decreases exponentially. The cost of a factory (“fab”) increases exponentially (now a few billion $).

7 Gate oxide has shrunk to < 2nm, < 10 atom layers. Electrons can tunnel through when applying a gate voltage. Uses up to 1 / 3 of the power. Power consumption by a leaky gate oxide: A show-stopper for Moore’s Law ?

8 Semiconductor-Insulator Interfaces : From the MOSFET to Molecular Electronics Mismatch of the bond density at the Si/SiO 2 interface

9 The Si/SiO 2 Interface Intermediate oxidation states at the interface provide a gradual transition from Si to SiO 2.

10 STEM + electron energy loss measurement across the Si/SiO 2 interface (see Lect. 5, Slides 16,17) 0.7 nm Limit Predicted for the Gate Oxide Thickness Intermediate oxides insulate poorly Si2p CBM

11 Intel is already at the limit: 0.8 nm oxide reached in demos Need gate insulator with high dielectric constant : HfO 2 Thicker oxide with same capacitance and less leakage

12

13 Atomic Layer Epitaxy (ALE) for Monolayer Control “Digital Growth” General concept of ALE: Adsorb fairly inert pre- cursor molecules onto a reactive sbstrate, such that only one monolayer sticks. Reactivate the surface by chemical treatment. Repeat this cycle. ALE growth of Al 2 O 3 (alumina) from an organo-metallic precursor with reactivation by H 2 O.

14 Molecular Field Effect Transistors Molecular Control of Gate Dielectric and its Interface Review: Malliaras and Friend, Physics Today, May 2005, p. 5 Halik et al., Nature 431, 963 (2004) Si-Molecule Interfaces

15 Peters et al., Langmuir 18, 1250 (2002) Attaching Alkanes to Silicon via Siloxane Chemistry Moist  Ordered Dry  Disordered Silicon Alkane Cl HOHO C-H C-C OTS

16 In Pursuit of the Ultimate Storage Medium 1 bit = 1 atom 10  m 10 nm CD-ROM Silicon Surface Density x 10 6 Track spacing 5 atom rows Bennewitz et al. Nanotechnology 13, 499 (2002)

17 250 Terabit/inch 2 Year 2038 When will we be down to atoms ? Using Moore's Law...

18 CCD (Charge Coupled Device) Physics Nobel Prize 2009: Boyle and Smith The CCD detectors in digital cameras wiped out photographic film.

19 Operation of a CCD CCD detectors are based on silicon MOS technology (compare Slides 4, 5). Each pixel consists of a MOS capacitor with positive gate voltage. Contrary to a MOSFET, electrons cannot flow directly into the channel. Only those excited by photons are able to charge the capacitor, building up a charge bucket. Readout: Charge buckets are shifted along a row of pixels (“bucket brigade”). GateChannel VB CB


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