5 Cont..- Memory is considered consists of a number of fixed-length blocks of K words each. There are M=2n/K blocks.- The cache consists of C lines and each lines contains K words, plus a tag of a few bits. The number of words in the line is referred to as the line size and the number of lines is less than the number of main memory blocks.Some subset of the blocks of memory resides in lines in the cache. If a word in a block of memory is read, that block is transferred to one of the lines of the cache. Because there are more blocks than lines, an individual line cannot be uniquely and permanently dedicated to a particular block.Each line includes a tag that identifies which particular block is currently being stored.
6 Cache operation – overview CPU requests contents of memory locationCheck cache for this dataIf present, get from cache (fast)If not present, read required block from main memory to cacheThen deliver from cache to CPUCache includes tags to identify which block of main memory is in each cache slot
11 Comparison of Cache Sizes Comparison of Cache SizesProcessorTypeYear of IntroductionL1 cacheaL2 cacheL3 cacheIBM 360/85Mainframe196816 to 32 KB—PDP-11/70Minicomputer19751 KBVAX 11/780197816 KBIBM 303364 KBIBM 30901985128 to 256 KBIntel 80486PC19898 KBPentium19938 KB/8 KB256 to 512 KBPowerPC 60132 KBPowerPC 620199632 KB/32 KBPowerPC G4PC/server1999256 KB to 1 MB2 MBIBM S/390 G41997256 KBIBM S/390 G68 MBPentium 42000IBM SPHigh-end server/ supercomputer64 KB/32 KBCRAY MTAbSupercomputerItanium200116 KB/16 KB96 KB4 MBSGI Origin 2001High-end serverItanium 220026 MBIBM POWER520031.9 MB36 MBCRAY XD-1200464 KB/64 KB1MBa Two values seperated by a slash refer to instruction and data cachesb Both caches are instruction only; no data caches
12 Mapping Function Cache of 64kByte Cache block of 4 bytes i.e. cache is 16k (214) lines of 4 bytes16MBytes main memory24 bit address(224=16M)
13 Direct Mapping Each block of main memory maps to only one cache line i.e. if a block is in cache, it must be in one specific placeAddress is in two partsLeast Significant w bits identify unique wordMost Significant s bits specify one memory blockThe MSBs are split into a cache line field r and a tag of s-r (most significant)
14 Direct Mapping Address Structure Tag s-rLine or Slot rWord w142824 bit address2 bit word identifier (4 byte block)22 bit block identifier8 bit tag (=22-14)14 bit slot or lineNo two blocks in the same line have the same Tag fieldCheck contents of cache by finding line and checking Tag
15 Direct Mapping Cache Line Table Cache line Main Memory blocks held0 0, m, 2m, 3m…2s-m1 1,m+1, 2m+1…2s-m+1m-1 m-1, 2m-1,3m-1…2s-1
18 Direct Mapping Summary Address length = (s + w) bitsNumber of addressable units = 2(s+w) words or bytesBlock size = line size = 2w words or bytesNumber of blocks in main memory =2(s+ w)/2w = 2sNumber of lines in cache = m = 2rSize of tag = (s – r) bits
19 Direct Mapping pros & cons SimpleInexpensiveFixed location for given blockIf a program accesses 2 blocks that map to the same line repeatedly, cache misses are very high
20 Associative MappingA main memory block can load into any line of cacheMemory address is interpreted as tag and wordTag uniquely identifies block of memoryEvery line’s tag is examined for a matchCache searching gets expensive
23 Associative Mapping Address Structure Word2 bitTag 22 bit22 bit tag stored with each 32 bit block of dataCompare tag field with tag entry in cache to check for hitLeast significant 2 bits of address identify which 16 bit word is required from 32 bit data blocke.g.Address Tag Data Cache lineFFFFFC FFFFFC FFF
24 Associative Mapping Summary Address length = (s + w) bitsNumber of addressable units = 2s+w words or bytesBlock size = line size = 2w words or bytesNumber of blocks in main memory = 2s+ w/2w = 2sNumber of lines in cache = undeterminedSize of tag = s bits
25 Set Associative Mapping Cache is divided into a number of setsEach set contains a number of linesA given block maps to any line in a given sete.g. Block B can be in any line of set ie.g. 2 lines per set2 way associative mappingA given block can be in one of 2 lines in only one set
26 Set Associative Mapping Example 13 bit set numberBlock number in main memory is modulo 213000000, 00A000, 00B000, 00C000 … map to same set
28 Set Associative Mapping Address Structure Tag 9 bitSet 13 bitWord2 bitUse set field to determine cache set to look inCompare tag field to see if we have a hite.gAddress Tag Data Set number1FF 7FFC 1FF FFF001 7FFC FFF
30 Set Associative Mapping Summary Address length = (s + w) bitsNumber of addressable units = 2s+w words or bytesBlock size = line size = 2w words or bytesNumber of blocks in main memory = 2dNumber of lines in set = kNumber of sets = v = 2dNumber of lines in cache = kv = k * 2dSize of tag = (s – d) bits
31 Replacement Algorithms (1) Direct mapping No choiceEach block only maps to one lineReplace that line
32 Replacement Algorithms (2) Associative & Set Associative Hardware implemented algorithm (speed)Least Recently used (LRU)e.g. in 2 way set associativeWhich of the 2 block is lru?First in first out (FIFO)replace block that has been in cache longestLeast frequently usedreplace block which has had fewest hitsRandom
33 Write PolicyMust not overwrite a cache block unless main memory is up to dateMultiple CPUs may have individual cachesI/O may address main memory directly
34 Write through All writes go to main memory as well as cache Multiple CPUs can monitor main memory traffic to keep local (to CPU) cache up to dateLots of trafficSlows down writes (creating bottleneck)Remember bogus write through caches!
35 Write back Updates initially made in cache only Update bit for cache slot is set when update occursIf block is to be replaced, write to main memory only if update bit is setOther caches get out of syncI/O must access main memory through cacheN.B. 15% of memory references are writes
36 Pentium 4 Cache 80386 – no on chip cache 80486 – 8k using 16 byte lines and four way set associative organizationPentium (all versions) – two on chip L1 cachesData & instructionsPentium III – L3 cache added off chipPentium 4L1 caches8k bytes64 byte linesfour way set associativeL2 cacheFeeding both L1 caches256k128 byte lines8 way set associativeL3 cache on chip
37 Processor on which feature first appears Intel Cache EvolutionProblemSolutionProcessor on which feature first appearsExternal memory slower than the system bus.Add external cache using faster memory technology.386Increased processor speed results in external bus becoming a bottleneck for cache access.Move external cache on-chip, operating at the same speed as the processor.486Internal cache is rather small, due to limited space on chipAdd external L2 cache using faster technology than main memoryContention occurs when both the Instruction Prefetcher and the Execution Unit simultaneously require access to the cache. In that case, the Prefetcher is stalled while the Execution Unit’s data access takes place.Create separate data and instruction caches.PentiumIncreased processor speed results in external bus becoming a bottleneck for L2 cache access.Create separate back-side bus that runs at higher speed than the main (front-side) external bus. The BSB is dedicated to the L2 cache.Pentium ProMove L2 cache on to the processor chip.Pentium IISome applications deal with massive databases and must have rapid access to large amounts of data. The on-chip caches are too small.Add external L3 cache.Pentium IIIMove L3 cache on-chip.Pentium 4
39 Pentium 4 Core Processor Fetch/Decode UnitFetches instructions from L2 cacheDecode into micro-opsStore micro-ops in L1 cacheOut of order execution logicSchedules micro-opsBased on data dependence and resourcesMay speculatively executeExecution unitsExecute micro-opsData from L1 cacheResults in registersMemory subsystemL2 cache and systems bus
40 Pentium 4 Design Reasoning Decodes instructions into RISC like micro-ops before L1 cacheMicro-ops fixed lengthSuperscalar pipelining and schedulingPentium instructions long & complexPerformance improved by separating decoding from scheduling & pipelining(More later – ch14)Data cache is write backCan be configured to write throughL1 cache controlled by 2 bits in registerCD = cache disableNW = not write through2 instructions to invalidate (flush) cache and write back then invalidateL2 and L3 8-way set-associativeLine size 128 bytes
41 PowerPC Cache Organization 601 – single 32kb 8 way set associative603 – 16kb (2 x 8kb) two way set associative604 – 32kb620 – 64kbG3 & G464kb L1 cache8 way set associative256k, 512k or 1M L2 cachetwo way set associativeG532kB instruction cache64kB data cache
43 ExerciseConsider a machine with a byte addressable main memory of 216 bytes and block size of 8 bytes. Assume that a direct mapped cache consisting of 32 lines is used with this machine.a) How is a 16-bit memory address divided into tag, line number,and byte number?b) Into what line would bytes with each of the following address bestored?c) Suppose the byte with address is storedin the cache. What are the address of other bytes stored alongwith it.
44 Cont.. d) How many total bytes of memory can be stored in the cache? e) Why is the tag also stored in the cache?