Presentation on theme: "Frontend of PHENIX Si pixel K. Tanida (RIKEN) FEM/DAQ meeting for PHENIX upgrade (10/24/02) Outline Overview of PHENIX Si pixel detector ALICE1 chip readout."— Presentation transcript:
Frontend of PHENIX Si pixel K. Tanida (RIKEN) FEM/DAQ meeting for PHENIX upgrade (10/24/02) Outline Overview of PHENIX Si pixel detector ALICE1 chip readout Pilot chip multi chip module ALICE PHENIX Things to be discussed/determined
Overview of PHENIX Si detector Innermost layer (2 layers) of barrel detector at r=2.5 cm (and 6 cm)
Pixel chip (ALICE1 chip) 32 x 256 pixels of 425 m (z) x 50 m (r ) size: 13.6 mm x 15.95 mm
Ladder structure 8 chips/ladder + 1 pilot 20 (50) ladders for 1st (2nd) layer 8192 x 8 x 20 (50) = 1.3 (3.2) Mchannel ladder pilot chip pixel chips data bus with chip select optical link cross section side view
ALICE1 chip readout 1 channel 1 bit (binary) 32 parallel lines, each reads 256 channels serially readout speed: 10 MHz 25.6 s/chip - ALICE reads 10 chips serially via pilot chip 256 s/event ALICE1 has data buffer for 4 events No data format (header, footer, parity bits...) - must be taken care at somewhere (FEM?)
Pilot chip multi chip module Takes care of readout, control (via JTAG), etc. ALICE PCMCM: Consists of 4 parts - Analog pilot (A), Digital pilot (D), GOL (G), and optical link driver (O) Analog pilot -- monitors temperature, etc. G + O drives G link. Bandwidth: 1.28 Gb/s Digital pilot -- main chip A D G O 15.5 mm 51 mm
ALICE PHENIX What are different? - readout time (256 s/event in ALICE, 40 or 80 s in PHENIX) - event buffer (4 in ALICE1, PHENIX requires 5) - zero suppresstion, data format (to be discussed in this meeting) - L1 trigger timing (5.5 s 4 s) is OK. Solution? - depends on readout time limit - parallelize readout (2 or more pilot chips in a ladder, sequential parallel readout, etc.) - development of our own pilot and/or other FEM necessary
Ladder Readout Scheme l CERN/ALICE: l pixel chip runs with 10 MHz l pilot chip runs with 40 MHz l One pilot per ladder l read 1 word from each chip l read 2 word from each chip l …. l Data stream ladder pilot chip pixel chip data bus with chip select marker word 1 chip 1 word 1 chip 2 word 1 chip 3 word 1 chip 4 word 1 chip 5 word 1 chip 6 word 1 chip 7 word 1 chip 8 word 2 chip 1 word 2 chip 2 ….. word 256 chip 8 25 ns (40 MHz) or 50 ns? 200 ns (5 MHz) ~ 52 s may need own pilot chip development! 100 MHz 21 s might fit in FPGA?
Things to be discussed/determined Readout time (40 or 80 s?/event) Data format and zero suppression scheme - What does it? Pilot, FEM, DCM? Pilot chip: use ALICE pilot or develop our own? - RIKEN is considering both options - KEK experts are interested in development Data bus to outside (optical link?): - ALICE G-link cannot handle 1.6 Gb/s (8 x 8192 bits in 40 s) - Size of optical link driver is the primary problem (less than 1 cm 2 necessary) - If electorical cables are used, FEM is a must.