1. SOC Consortium Course Material Memory Controller National Taiwan University Adopted from National Taiwan University SoC Design Laboratory

2. SOC Consortium Course Material 1 Goal of This Lab  Familiarize with ARM memory interface  Know ARM Integrator memory map well  How to access memory

3. SOC Consortium Course Material 2 Outline  The ARM Memory Interface [1]  ARM Integrator System Memory Map [2] [3]

4. SOC Consortium Course Material 3 Simple Memory Interface  The simplest form of memory interface is suitable for operation with ROM and static RAM (SRAM).  8-bit memory types, so four parts of each type are required to form a 32-bit memory.  Since the bottom two address lines, A[1:0], are used for byte selection, they are used by the control logic and not connected to the memory.  Although the ARM performs reads of both bytes and words, the memory system can ignore the difference and always simply supply a word quantity.

5. SOC Consortium Course Material 4 Basic ARM Memory System

6. SOC Consortium Course Material 5 Control Logic  It decides when to activate the RAM and when to activate the ROM –A[31] = 0 => access ROM –A[31] = 1 => access RAM  It controls the byte write enables during a write operation –Word write / half-word write / byte write  It ensures that the data is ready before the processor continues

7. SOC Consortium Course Material 6 Simple ARM Memory System Control Logic Write Read

8. SOC Consortium Course Material 7 Transfer Widths A[31]r/wmas[1]mas[0]A[1]A[0]Output signal 00××××ROMoe 01××××None 10××××RAMoe 1100×× None 1111×× 1110×× Word (RAMwe0, RAMwe1, RAMwe2, RAMwe3) 11010×Half word (RAMwe0, RAMwe1) 11011×Half word (RAMwe2, RAMwe3) 11××00Byte (RAMwe0) 11××01Byte (RAMwe1) 11××10Byte (RAMwe2) 11××11Byte (RAMwe3) Write Read

9. SOC Consortium Course Material 8 DRAM memory organization ras: row address strobecas: column address strobe

10. SOC Consortium Course Material 9 Outline  The ARM Memory Interface [1]  ARM Integrator System Memory Map [2][3]

11. SOC Consortium Course Material 10 Core Module Memory Map  The nMBDET signal is permanently grounded by the motherboard so that it is pulled LOW on the core module when it is fitted.  The REMAP bit only has effect if the core module is attached to a motherboard (nMBDET = 0).

12. SOC Consortium Course Material 11 Core Module Memory Map (cont.) 256MB 256KB 8MB

13. SOC Consortium Course Material 12 Core Module Alias Address

14. SOC Consortium Course Material 13 Memory Map for Core Module  REMAP = 0: Default following reset. Accesses to addresses 0x00000000 to 0x0003FFFF –S1[1] = ON: the access is to boot ROM –S1[1] = OFF: the access is to flash  REMAP = 1: Accesses to address 0x00000000 to 0x0003FFFF

15. SOC Consortium Course Material 14 System Memory Map (1/2)

16. SOC Consortium Course Material 15 System Memory Map (2/2)

17. SOC Consortium Course Material 16 References [1] http://access.ee.ntu.edu.tw/course/SOC_LAB/index.html [1] ARM System-on-Chip Architecture by S.Furber, Addison Wesley Longman: ISBN 0-201-67519-6. [2] DUI0098B_AP_UG.pdf. [3] DUI0126B_CM7TDMI_UG.pdf

18. SOC Consortium Course Material 17 Experiment Requirements  Try to compile the program of this experiment by using Thumb code to get the same result. Modify the memory usage if needed.  Make a table to show the statistics (memory and cycle requirement) about ARM codes and Thumb codes and compare their difference.