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Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience.

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Presentation on theme: "Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience."— Presentation transcript:

1 Digital System Clocking: High-Performance and Low-Power Aspects Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, Nikola M. Nedovic Wiley-Interscience and IEEE Press, January 2003 Chapter 9: Microprocessor Examples

2 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic2 Microprocessor Examples Clocking for Intel® Microprocessors IA-32 Pentium® Pro First IA-64 Microprocessor Pentium 4 Sun Microsystems UltraSPARC-III® Clocking Clocking and CSEs Alpha® Clocking: A Historical Overview Clocking and CSEs IBM® Microprocessors Level-Sensitive Scan Design Examples of CSEs

3 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic3 Microprocessor Examples Clocking for Intel® Microprocessors IA-32 Pentium® Pro First IA-64 Microprocessor Pentium 4 Sun Microsystems UltraSPARC-III® Clocking Clocking and CSEs Alpha® Clocking: A Historical Overview Clocking and CSEs IBM® Microprocessors Level-Sensitive Scan Design Examples of CSEs

4 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic4 Source: Microprocessor Report Journal Pentium  IIPentium  IIIPentium  4 MPR Issue June 1997April 2000Dec 2001 Clock Speed 266 MHz1GHz2GHz Pipeline Stages 12/14 22/24 Transistors 7.5M24M42M Cache (I/D/L2) 16k/16K/-16K/16K/256K12K/8K/256K Die Size 203mm 2 106mm 2 217mm 2 IC Process 0.28  m, 4M0.18  m, 6M Max Power 27W23W67W Intel® Microprocessor Features

5 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic5 Clock distribution network with deskewing circuit (Geannopoulos and Dai 1998), Copyright © 1998 IEEE IA-32 Pentium® Pro

6 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic6 Delay shift register (Geannopoulos and Dai 1998), Copyright © 1998 IEEE IA-32 Pentium® Pro

7 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic7 Phase detector (Geannopoulos and Dai 1998), Copyright © 1998 IEEE IA-32 Pentium® Pro

8 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic8 Clock distribution topology (Rusu and Tam 2000), Copyright © 2000 IEEE First IA-64 Microprocessor

9 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic9 Deskew buffer architecture (Rusu and Tam 2000), Copyright © 2000 IEEE First IA-64 Microprocessor

10 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic10 Digitally controlled delay line (Rusu and Tam 2000), Copyright © 2000 IEEE First IA-64 Microprocessor

11 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic11 Simulated regional clock-grid skew (Rusu and Tam 2000), Copyright © 2000 IEEE First IA-64 Microprocessor

12 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic12 Measured regional clock skew (Rusu and Tam 2000), Copyright © 2000 IEEE First IA-64 Microprocessor

13 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic13 Core and I/O clock generation (Kurd et al. 2001), Copyright © 2001 IEEE Pentium® 4

14 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic14 Logical diagram of core clock distribution (Kurd et al. 2001), Copyright © 2001 IEEE Pentium® 4

15 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic15 Example of local clock buffers generating various frequency, phase and types of clocks (Kurd et al. 2001), Copyright © 2001 IEEE Pentium® 4

16 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic16 Microprocessor Examples Clocking for Intel® Microprocessors IA-32 Pentium® Pro First IA-64 Microprocessor Pentium 4 Sun Microsystems UltraSPARC-III® Clocking Clocking and CSEs Alpha® Clocking: A Historical Overview Clocking and CSEs IBM® Microprocessors Level-Sensitive Scan Design Examples of CSEs

17 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic17 UltraSPARC-I®UltraSPARC-II®UltraSPARC-III® Year199519972000 ArchitectureSPARC V9, 4-issue Die size17.7x17.8mm 2 12.5x12.5mm 2 15x15.5mm 2 # of transistors5.2M5.4M23M Clock Frequency167MHz330MHz1GHz Supply voltage3.3V2.5V1.6V Process 0.5  m CMOS0.35  m CMOS0.15  m CMOS Metal layers4 (Al)5 (Al)7 (Al) Power consumption <30W <80W UltraSPARC® Family Characteristics

18 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic18 Clock distribution delay in UltraSPARC-III (Heald et al. 2000), Copyright © 2000 IEEE UltraSPARC-III®: Clocking

19 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic19 Semidynamic flip-flop (Klass 1998), Copyright © 1998 IEEE UltraSPARC-III: Clock Storage Elements

20 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic20 (a)Logic embedding in a semidynamic flip-flop; (b)Two-input XOR function. (Klass, 1998), Copyright © 1998 IEEE UltraSPARC-III: Clock Storage Elements

21 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic21 Dynamic versions of semidynamic flip-flop: single-ended; Differential. (Klass 1998), Copyright © 1998 IEEE UltraSPARC-III: Clock Storage Elements

22 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic22 UltraSPARC-III flip-flop (Heald et al. 2000), Copyright © 2000 IEEE UltraSPARC-III: Clock Storage Elements

23 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic23 Microprocessor Examples Clocking for Intel® Microprocessors IA-32 Pentium® Pro First IA-64 Microprocessor Pentium 4 Sun Microsystems UltraSPARC-III® Clocking Clocking and CSEs Alpha® Clocking: A Historical Overview Clocking and CSEs IBM® Microprocessors Level-Sensitive Scan Design Examples of CSEs

24 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic24 21064211642126421364 # transistors [M] 1.689.315.2152 Die Size [mm 2 ] 16.8x13.918.1x16.516.7x18.821.1x18.8 Process 0.75  m0.5  m0.35  m0.18  m Supply [V] 3.3 2.21.5 Power [W] 305072125 Clk Freq. [MHz] 2003006001200 Gates/Cycle 161412 Alpha® Microprocessor Features

25 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic25 Alpha microprocessor final clock driver location: (a) 21064, (b) 21164, (c) 21264 (a)(b)(c) Alpha® Microprocessors: Clocking

26 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic26 21064 clock skew (Gronowski et al. 1998), Copyright © 1998 IEEE Alpha® Microprocessors: Clocking

27 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic27 21164 clock skew (Gronowski et al. 1998), Copyright © 1998 IEEE Alpha® Microprocessors: Clocking

28 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic28 21264 clock hierarchy (Gronowski et al. 1998), Copyright © 1998 IEEE Alpha® Microprocessors: Clocking

29 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic29 21264 clock skew (Gronowski et al. 1998), Copyright © 1998 IEEE Alpha® Microprocessors: Clocking

30 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic30 21364 major clock domains (Xanthopoulos et al. 2001), Copyright © 2001 Alpha® Microprocessors: Clocking

31 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic31 21364, NCLK clock skew (Xanthopoulos et al. 2001), Copyright © 2001 IEEE Alpha® Microprocessors: Clocking

32 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic32 21064 modified TSPC latches (Gronowski et al. 1998), Copyright © 1998 Alpha® µ P: Clock Storage Elements

33 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic33 21164: (a) phase-A latch, (b) phase-B latch (Gronowski et al. 1998), Copyright © 1998 IEEE (a)(b) Alpha® µ P: Clock Storage Elements

34 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic34 Embedding of logic into a latch: (a) 21064 TSPC latch, one level of logic; (b) 21164 latch, two levels of logic. (Gronowski et al. 1998), Copyright © 1998 IEEE (a)(b) Alpha® µ P: Clock Storage Elements

35 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic35 21264 flip-flop (Gronowski et al. 1998), Copyright © 1998 IEEE Alpha® µ P: Clock Storage Elements

36 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic36 Critical-path and race analysis for clock buffering and conditioning (Gronowski et al. 1998), Copyright © 1998 IEEE Alpha® Microprocessors: Timing

37 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic37 Microprocessor Examples Clocking for Intel® Microprocessors IA-32 Pentium® Pro First IA-64 Microprocessor Pentium 4 Sun Microsystems UltraSPARC-III® Clocking Clocking and CSEs Alpha® Clocking: A Historical Overview Clocking and CSEs IBM® Microprocessors Level-Sensitive Scan Design Examples of CSEs

38 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic38 Eichelberger 1983 Hazard-Free Level-Sensitive Polarity-Hold Latch

39 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic39 General LSSD Configuration

40 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic40 LSSD Shift Register Latch

41 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic41 LSSD Double Latch Design

42 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic42 LSSD SRL with multiplexer used in the IBM S/390 G4 processor (Sigal et al. 1997), reproduced by permission IBM® S/390 Parallel Server Processor

43 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic43 Static multiplexer version of the SRL used in the IBM S/390 G4 (Sigal et al. 1997), reproduced by permission IBM® S/390 Parallel Server Processor

44 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic44 A clocked storage element is used in the non-timing-critical timing macros of the IBM S/390 G4 processor (Sigal et al. 1997), reproduced by permission IBM® S/390 Parallel Server Processor

45 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic45 The clock-generation element used to detect problems created with fast paths: IBM S/390 G4 processor (Sigal et al. 1997), reproduced by permission IBM® S/390 Parallel Server Processor

46 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic46 The experimental IBM PowerPC processor (Silberman et al. 1998), reproduced by permission IBM® PowerPC Processor

47 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic47 The PowerPC 603 MSL (Gerosa et al. 1994), Copyright © 1994 IEEE IBM® PowerPC 603: Master-Slave Latch

48 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic48 The PowerPC 603 local clock regenerator (Gerosa et al. 1994), Copyright © 1994 IEEE IBM® PowerPC 603: Local Clk Generator

49 Nov. 14, 2003Digital System Clocking: Oklobdzija, Stojanovic, Markovic, Nedovic49 Summary Intel® Microprocessors Active clock deskewing in Pentium® processors Sun Microsystems® Processors Semidynamic flip-flop (one of the fastest single-ended flip-flops today, “soft-edge”) Alpha® Processors Performance leader in the ‘90s Incorporating logic into CSEs IBM® Processors Design for testability techniques Low-power champion PowerPC 603

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