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Casper Signal Processing Workshop 2009 SKA Signal Processing (Preliminary) Wallace Turner Domain Specialist for Signal Processing.

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Presentation on theme: "Casper Signal Processing Workshop 2009 SKA Signal Processing (Preliminary) Wallace Turner Domain Specialist for Signal Processing."— Presentation transcript:

1 Casper Signal Processing Workshop 2009 SKA Signal Processing (Preliminary) Wallace Turner Domain Specialist for Signal Processing

2 SPDO Example Configuration (Phase 2) 2 of 35 Memo 100 identifies the following options: 70-200MHz: Sparse AA 200-500MHz: Sparse AA 500MHz-10GHz: 3000 15m dishes Or 500MHz- 10GHz: 2000 15m dishes with PAFs plus WBSPF Or 500MHz-10GHz: 250 Dense AA plus 2400 15m dishes/ WBSPF Note: On going discussions 15m vs 12m dishes Example Configuration with Dense AA + SPF

3 SPDO Reference Design 3 of 35

4 SPDO Dishes+Single Pixel Feeds 4 of 35 American: 6m Hydroformed DishSouth Africa: 15m Composite Dish Canadian: 10m Composite Dish Note: On going discussions 12m vs. 15m dish Required sensitivity 10,000 m 2 K -1 Correlator processor and dump rate proportional to N ant 2 ADC likely to be at antenna (4 bit ?) O/P rate = fs.4bits = 160 G bits/s per antenna Where fs = sample rate likely to be split into smaller basebands

5 SPDO AGN Science Chapter Example 5 of 35 AGN Science Chapter Survey Speed: 1 x 10 5 m 4 K -2 deg 2 Frequency range 500 MHz to 8GHz Tsys now: Not achieved over bandwidth Target Tsys: 35K

6 SPDO Dishes+Phased Array Feeds 6 of 35 Apertif Netherlands: Vivaldi Array ASKAP Australia: Checkerboard Array PHAD Canada: Vivaldi Array Note: Some Channelization and Beamforming likely to be at antenna. Maximum Field of View limited by Array size and focal length of dish. Achievable field of view limited by network bandwidth.

7 SPDO Example Number PAFs Required 7 of 35 Wide Field Polarimetry Science Chapter Survey Speed: 5 x 10 8 m 4 K -2 deg 2 Max frequency 2GHz WBSPF would require over 15,000 dishes Tsys now: 100 K Target Tsys: 50 K

8 SPDO Simplistic View of PAF Processing Consider Frequency Domain Beamforming Channelisation: N chan ~ 64 –12 taps gives < 60db aliasing between channels –Processing load ~ (N taps + 3 * log 2 (N chan )) x N el x 2pol x f s –N taps = 12, N el = 96 x 2pol & f s = 1.4 GHz for 700MHz bandwidth Processing load= 8 x 10 12 MACS Beamformer (per antenna): –Average beams per channel 30 –Processing Load = N bms.N el.2pol.f s. 4Multiplies = 3 x 10 13 Macs O/P rate = N bms.2pol.f s.4bits.8B10B = 420 G bit/s –42 10 G bit/s optical cables per antenna –Includes 25 % extra bandwidth required for 8B/10B Encoding 2000 dishes with PAFs (total 840 T bits/s) Note :*FFT implementation dependent 8 of 35

9 SPDO Sparse Aperture Arrays 9 of 35 LOFAR: Netherlands et al LWA: USAMWA: USA & Australia Note: Two types of sparse AA required: 70MHz – 200 MHz 200MHz – 500 MHz Only solution for EoR HI Science Chapter

10 SPDO Dense Aperture Array Station 10 of 35 Assumed Dense Aperture Array ~256 tiles x 256 elements per tile 2 polarisations per element Sample rate ~ 2.5 G Hz 4 bits/ sample 56 m diameter 250 stations Tsys now 120K Target 35K Memo 100 Processing Bunker Dense AA Detail 300MHz to 1GHz i.e. 700MHz bandwidth fs=2 x 700 MHz 56m diameter array =>2463 m 2 44.4 2pol elements per m^2 (30 cm wavelength) = 110,000 elements x 2pol per station, about 2 x 64k elements. Array efficiency 80%, Bore efficiency 75% & Tsys = 35K -> 250 stations for 10,000m 2 K -1 sensitivity

11 SPDO Simplistic View of Dense Aperture Array Processing Consider Frequency Domain Beamforming –Delay is implemented as a phase slope in frequency domain. –Alternative time domain with tuned lengths of co-ax. Channelisation: N chan 1024, – 12 taps gives < 60db aliasing between channels –N taps = 12, N ant = 64k x 2pol & f s = 1.4 GHz for 700MHz bandwidth –Processing ~ (N taps + 3 * log 2 (N chan )) x N ant x 2pol x f s** =8 x 10 15 MACS Beamformer (per station): –Average 1437 beams per channel to cover 250 sq degrees FoV –Processing Load = N ant.2pol.N bms.f s. 4MACS = 1 x 10 18 MACS O/P rate** = N bms.2 pol.f s.4bits.8B10B = 20 T bit/s –Over 2000 10 G bit/s optical cables, 8B/10B Encoding factor 1.25 Up to 250 Dense AA Stations (total 10 peta bits/s) Note :*FFT implementation dependent **Ignores upsampling of channelizer 11 of 35

12 SPDO Correlator Processing Loads Channelisation (700MHz bandwidth): –SPF 4 x 10 14 (10 5 channels) –PAF 4 x 10 12 (4096 fine channels giving ~ 10 5 total) –Dense AA 6 x 10 15 (128 fine channels ~ 10 5 total) Correlation load (700 MHz bandwidth) –SPF load = 6 x 10 16 MACS –PAF load = 1 x 10 18 MACS –Dense AA = 2 x 10 18 MACS Correlator Dump Rate (Dish Solution) – 2280 15 m dishes + 40 x 18 dish stations and 3000 km baseline: –Integration time ~ 200ms for < 1% smearing 5 x 10 6 /2 baselines x 10 5 channels x 4 bytes x 5 Hz = 9 T Bytes/s Not calculated for other configurations yet 12 of 35

13 SPDO Signal Processing Overview Memo 100 Option a* 13 * Sparse AAs + 3000 15-m dishes with SPFs

14 SPDO Signal Processing Overview Memo 100 option b* 14 of 35 * Sparse AAs + 2400 15-m dishes with PAFS & WBSPF Possibly include a beam former for the core

15 SPDO Signal Processing Overview Memo 100 option c* 15 of 35 * Sparse AAs + 250 Dense AA + 2000 15-m dishes with SPFs

16 SPDO Technology Options FPGA –Virtex 6 (available 2010): 2016 x DSP slices clocked at 600 MHz -> 1200 G MACS ~ 25 G MACs per Watt 10 18 MACS requires ~ 10 6 FPGAS => 48 W per device and ~ 48 M Watts for 10 18 MACS Operating cost 1$ per Watt per year => $48M per annum Plus cost of cooling and delivering power ASIC –22nm (available 2010): 2.5 nW/MHz/Gate > 40 T MACS (4 bit) per device => 25,000 devices Assuming < 50 % gates switching at any one time: 600kW Operating cost $600k per annum 16 of 35

17 SPDO What would F or X unit look like? 17 of 35 Baseline Board (front) Station BoardBaseline Board (rear) Pictures courtesy Brent Carlson EVLA style boards might be an optiton ? 64 ASICS or FPGAs on board (~1.5 kW card) ~ 190 boards for Dense AA ASIC correlator 14 cards per shelf -> 14 shelves Is production yield an issue? Could use smaller 8 processor chip board As per ASKAP or Uniboard Inter-board Communication links increase

18 SPDO Multichip Module 18 of 35 SKADS have developed a promising Multichip Module: 4 x 4 antenna array currently, Current RFI Protection shows -57dB per M (in air) Picture courtesy of Kris Zarb Adami Could be developed and used in several areas of the SKA (Note that the key components are ADC and Optical I/O, although the others could be useful in some applications.)

19 SPDO Correlator Centre Build Cost 19 of 35 Kevin Wohlever 2006 ASIC solution 1 cabinet per 30 sq ft Between 80 & 160 cabs? Factor of 4 for air con &PSU units, offices ~ 50 W per sq ft

20 SPDO SPDO Team Project DirectorRichard Schilizzi Project Engineer Peter Dewdney Executive OfficerColin Greenwood Project ScientistJoe Lazio System EngineerKobus Cloete Domain Specialist Receptors Neil Roddis Domain Specialist Signal TransportRoshene McCool Domain Specialist Computing & SoftwareDuncan Hall Domain Specialist Signal ProcessingWallace Turner Site EngineerRob Millenaar Project Management OfficerBilly Adams Industry Relations ManagerPhil Crosby Office ManagerLisa Bell 20


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