1. הפקולטה למדעי ההנדסה Faculty of Engineering Sciences

2. 6T SRAMBitcell DesignArchitectureSummaryIntroduction Introduction Introduction SRAM Overview SRAM Overview Novel SRAM bitcell Novel SRAM bitcell Test Chip Architecture Test Chip Architecture Summary Summary

3. 6T SRAMBitcell DesignArchitectureSummaryIntroduction Memory is classified by 4 major categories Volatility, Access Speed, Capacity and Cost VolatileNon Volatile

4. 6T SRAMBitcell DesignArchitectureSummaryIntroduction Minimum energy point in digital circuits is achieved at subthreshold voltages (Vdd < Vt). Minimum energy point in digital circuits is achieved at subthreshold voltages (Vdd < Vt). Low-voltage operation of SRAM memories in the subthreshold region offers substantial power and energy savings at the cost of speed. Low-voltage operation of SRAM memories in the subthreshold region offers substantial power and energy savings at the cost of speed. This project focuses on the design and implementation of a novel SRAM bitcell for use in the subthreshold region. This project focuses on the design and implementation of a novel SRAM bitcell for use in the subthreshold region.

5. 6T SRAMBitcell DesignArchitectureSummaryIntroduction

6. 6T SRAMBitcell DesignArchitectureSummaryIntroduction Bistability Principle (Q, QB) Bistability Principle (Q, QB) Differential Read (Sense Amp) Differential Read (Sense Amp) Fast Access Speeds (read, write) Fast Access Speeds (read, write) Differential Write Differential Write Large Noise Margins Large Noise Margins Large Area (6 transistors) Large Area (6 transistors) Prechargable Bitlines Prechargable Bitlines Power Consuming Power Consuming

7. 6T SRAMBitcell DesignArchitectureSummaryIntroduction Positive feedback creates two stable points “1” and “0”. Positive feedback creates two stable points “1” and “0”. Regenerative property ensures a noisy cell converges back to nominal values. Regenerative property ensures a noisy cell converges back to nominal values.

8. 6T SRAMBitcell DesignArchitectureSummaryIntroduction 1.Bitlines (BL, BL’) are precharged to VDD 2.Wordline signal (WL) is asserted 3.One of the bitlines is pulled down toward GND. 4.Differential signal (BL-BL’) is amplified to accelerate the process. M 1 > M 5 Constraint!

9. 6T SRAMBitcell DesignArchitectureSummaryIntroduction 1.Bitlines are precharged to complementary values. 2.Worldline signal (WL) is asserted. 3.Q is pulled down to GND while Q’ is driven to VDD. M 6 > M 4 Constraint!

10. 6T SRAMBitcell DesignArchitectureSummaryIntroduction In general, ratioed digital circuits are more likely to fail in subthreshold voltages. In general, ratioed digital circuits are more likely to fail in subthreshold voltages. 6T Bitcells cannot operate below 600mV – 700mV. 6T Bitcells cannot operate below 600mV – 700mV. Read SNM problem - degraded read noise margins decrease bitcell stability. Read SNM problem - degraded read noise margins decrease bitcell stability. Write fails under 600mV due to the increase of the pMOS drive in sub-threshold. Write fails under 600mV due to the increase of the pMOS drive in sub-threshold.

11. 6T SRAMBitcell DesignArchitectureSummaryIntroduction

12. 6T SRAMBitcell DesignArchitectureSummaryIntroduction Numerous novel low-power SRAM memories have been proposed in recent years. Numerous novel low-power SRAM memories have been proposed in recent years. We studied and analyzed many of the important proposals which include : 6T, 7T, 8T, 9T, 10T bitcells, Virtual VDD, Virtual GND, DCVSL, Voltage Boost, Read Buffer, Read Assist, Voltage Boost, and more ……. We studied and analyzed many of the important proposals which include : 6T, 7T, 8T, 9T, 10T bitcells, Virtual VDD, Virtual GND, DCVSL, Voltage Boost, Read Buffer, Read Assist, Voltage Boost, and more …….

13. 6T SRAMBitcell DesignArchitectureSummaryIntroduction

14. 6T SRAMBitcell DesignArchitectureSummaryIntroduction

15. 6T SRAMBitcell DesignArchitectureSummaryIntroduction MC Functionality Simulations MC Performance Tests MC optimizations MC layout Test Chip Architecture Design Full Chip(8-kb Array) Layout Post Layout Simulations TAPEOUT!

16. 6T SRAMBitcell DesignArchitectureSummaryIntroduction Schematic of a standard 8T SRAM bitcellStick Diagram of a standard 8T SRAM bitcell

17. 6T SRAMBitcell DesignArchitectureSummaryIntroduction

18. 6T SRAMBitcell DesignArchitectureSummaryIntroduction WBL is driven to “1” and WBLB to “0” Write wordline (enable) is asserted Q is driven to “1” and QB to “0” Q is discharged to during standby CLK synchronizes write access

19. 6T SRAMBitcell DesignArchitectureSummaryIntroduction 1.35X

20. 6T SRAMBitcell DesignArchitectureSummaryIntroduction Enables subthreshold write with a Virtual- VDD technique – weakening the Supply VDD during write operation. Enables subthreshold write with a Virtual- VDD technique – weakening the Supply VDD during write operation. A new approach for the design of the Virtual- VDD scheme reduces periphery and thus, reduces write power. A new approach for the design of the Virtual- VDD scheme reduces periphery and thus, reduces write power. Operates at ultra-low voltages, down to 200mV. Operates at ultra-low voltages, down to 200mV.

21. 6T SRAMBitcell DesignArchitectureSummaryIntroduction Schematic of a standard 8T SRAM bitcellStick Diagram of a standard 8T SRAM bitcell

22. 6T SRAMBitcell DesignArchitectureSummaryIntroduction

23. 6T SRAMBitcell DesignArchitectureSummaryIntroduction

24. 6T SRAMBitcell DesignArchitectureSummaryIntroduction 8-kb Array 8-kb Array Read-Bitline division Read-Bitline division Level Shifters Level Shifters Row Decoder Row Decoder Sense-Amps Sense-Amps Precharge Units Precharge Units Write Drivers Write Drivers BIST BIST

25. 6T SRAMBitcell DesignArchitectureSummaryIntroduction Schematic of Sensing Unit + Up Shifter Schematic of Write Driver Schematic of WL Driver + Down Shifter

26. 6T SRAMBitcell DesignArchitectureSummaryIntroduction 1.40 mm 1.40 um 2.90 um

27. 6T SRAMBitcell DesignArchitectureSummaryIntroduction SRAM access is synchronized by a clock. Bitline Precharge, write driving and digital logic execute during the high phase and read/write take place during the low phase.

28. 6T SRAMBitcell DesignArchitectureSummaryIntroduction

29. 6T SRAMBitcell DesignArchitectureSummaryIntroduction A fully functional 8-kb array was layed out and designed for the 40nm lp TSMC process. A fully functional 8-kb array was layed out and designed for the 40nm lp TSMC process. SFSRAM Memory successfully operates at subthreshold voltages - no additional periphery required. SFSRAM Memory successfully operates at subthreshold voltages - no additional periphery required. Additional power savings can be achieved in the PSRAM with a majority bit algorithm. Additional power savings can be achieved in the PSRAM with a majority bit algorithm.

30. 6T SRAMBitcell DesignArchitectureSummaryIntroduction

31. 6T SRAMBitcell DesignArchitectureSummaryIntroduction Digital Chip Chocolate Chip