1. RX Voltage Detection Circuit (LVD) and Power-On Reset (POR)
Hello and welcome to this Renesas Interactive module that provides an overview of the RX Voltage Detection Circuit and Power-On Reset
Ver. 1.00
© 2011 Renesas Electronics America Inc. All rights reserved.

2. Course Introduction Purpose Learn RX reset sources & voltage detection
Content
Voltage Detection Circuit (LVD)
LVD Control & Status Registers
RX Reset Sources
Determining Reset Source
Learning Time
20 Minutes
The purpose of this Renesas Interactive module is to give you a basic understanding of the RX voltage detection circuit and sources of reset
We’ll cover the voltage detection circuit, or LVD
LVD control & status registers
Source of reset on the RX and how to determine which source was the cause of a reset
This module should take about 20 minutes to complete
© 2011 Renesas Electronics America Inc. All rights reserved.

3. RX Voltage Detection Circuit (LVD)
Monitors Vcc voltage level
Interrupt and/or reset at two fixed voltages: Vdet1 & Vdet2
Off at power up by default
Key code register protects against unwanted modification
Vcc
Vdet2
Vdet1
Reset
VPOR
First, let’s look at the RX Voltage Detection Circuit, or LVD.
The LVD monitors the supply voltage to the RX looking for dips or sags. VCC is compared to two threshold voltages, Vdet1 and Vdet2. Both of these voltages are above the Power-On Voltage needed to bring the part out of reset.
The LVD can be configured to create two different types of events when VCC drops below the threshold voltages. An interrupt can be generated at either threshold, here we’re showing an interrupt being generated at the higher threshold: Vdet2. And the LVD can pull the chip into a reset state as well. Here we show the voltage continuing to drop below Vdet1 which has been configured to generate a reset.
If the voltage recovers and rises back above the threshold, the reset state is maintained until the voltage stays above the threshold for the Power-On Reset delay, shown as tPOR in the diagram. The Electrical Characteristics section of the hardware manual specifies the voltage levels and time delays shown.
Your code must enable the Voltage Detection Circuit; it is off by default. It’s also important to note that the LVD is protected by a Key Code Register that prevents inadvertent changes to the settings. Let’s see how.
© 2011 Renesas Electronics America Inc. All rights reserved.

4. LVD Key Code Register LVD Key Code Register (LVDKEYR)
Enables writing to LVD Control Register (LVDCR)
Write 0x3C to enable writing
Other values lock out changes
Locked on reset b7
After reset
LVD Key Code Register (LVDKEYR) b6 b5 b4 b3 b2 b1 b0
Because low supply voltages can cause erratic behavior in MCU’s, the settings for the Voltage Detection Circuit are protected by the LVD Key Code Register.
The LVD Key Code Register, show here, protects unwanted changes to the LVD settings. It control access to a single register, the LVD Control Register which we’ll see in a minute.
Writing a value of hex 0x3C to this register unlocks the LVD Control Register. Write any other value to protect you settings.
The LVD Key Code Register is in the locked state by default after reset; you’ll need to write the unlock code to it before you can enable the Voltage Detection Circuit.
© 2011 Renesas Electronics America Inc. All rights reserved.

5. Low-Voltage Detection Control Register
LVD Control Register (LVDCR)
LVD1E, LVD2E
Enable bits for LVD1 and LVD2 (1 = enabled)
LVD1RI, LV2RI
Selects interrupt or reset generation for each
0=Reset, 1=Interrupt
Interrupts are NMI’s (set NMIER.LVDEN in the ICU)
LVD1 and LVD2 are locked & disabled after reset
Lock it after changes with LVDKEYR!
LVD2E b7
After reset
LVD Control Register (LVDCR)
LVD2RI
---
LVD1E
LVD1RI b6 b5 b4 b3 b2 b1 b0
This brings us to the Low-Voltage Detection Control Register or LVDCR. It configures the operation of the LVD.
There are enable bits for each threshold voltage. Writing a 1 to the LVD1E or LVD2E bits enables the corresponding voltage comparator
A second bit for each threshold configures whether an interrupt or a reset is generated at the threshold voltage. Write a 0 to reset the chip when the voltage drops below the corresponding voltage, or a 1 to generate an interrupt.
Interrupts generated by the LVD are non-maskable interrupts. You’ll need to enable the interrupt in the NMI Enable Register in the ICU by setting the LVDEN bit. Once armed, the LVD interrupt cannot be disabled.
Remember that the LVD is disabled by default, and it’s settings are locked. So you need to unlock it and enable it before using it.
Finally, remember to always lock the register immediately after making changes.
© 2011 Renesas Electronics America Inc. All rights reserved.

6. Reset Status Register Reset Status Register (RSTR) LVD1F, LVD2F
Indicate state of LVD1 and LVD2 (1=detected)
PORF
0=Reset caused by something other than POR
1=POR was detected
DPSRSTF
Indicates reason for exit from deep software stby mode
DPSRSTF b7
After reset
Reset Status Register (RSTR)
---
LVD2F
LVD1F
PORF b6 b5 b4 b3 b2 b1 b0
The Reset Status Register allows software to determine why the processor was reset. There are four flags in the register.
LVD1F and LVD2F are set if the supply voltage dropped below either of the LVD thresholds
The PORF bit is set if a power-on-reset occurred, and cleared otherwise.
And the DPSRSTF bit indicates that a reset-induced wakeup from Deep Software Standby Mode occurred.
© 2011 Renesas Electronics America Inc. All rights reserved.

7. RX Resets Power-on reset Pin reset Voltage-monitoring
Deep software standby reset
Independent watchdog timer
Watchdog timer
Now let’s see the sources that can reset the RX.
There are:
-Power on resets
-Pin resets
-LVD resets that we already discussed
-A reset used to exit Deep Software Standby mode,
-And resets generated by two watchdog timers: the independent watchdog timer and the watchdog timer.
Let’s look at each of these briefly
© 2011 Renesas Electronics America Inc. All rights reserved.

8. Power-on reset Generated internally
RES# pin high when power is applied
VCC rises above VPOR (2.58V typ.)
Power-on reset time (tPOR) of 20-50ms (35 ms typ.)
RSTSR.PORF = 1
Don’t place capacitor on RES# line!
The RX has a built-in power-on reset circuit eliminating the need for external reset generators.
To use the internally generated power-on reset, simply connect the reset pin of the MCU to VCC through a pull-up resistor. This will ensure that the reset pin is high when VCC is applied, enabling the POR circuit.
Once the supply voltage rises above the power-on voltage threshold, the power-on-reset starts.
During POR, the reset circuit holds the part in reset for a short delay, typically 35ms, to allow the supply to stabilize.
After the tPOR delay, the part is released from reset and begins to run, and the PORF flag in the Reset Status Register (seen earlier) is set indicating a power-on-reset.
Because the POR circuit relies on having Reset high concurrently with VCC, don’t place a capacitor on the reset pin. This will slow the rise time of Reset in relation to VCC, preventing the POR circuit from properly recognizing the power-on condition.
© 2011 Renesas Electronics America Inc. All rights reserved.

9. Pin Reset Drive RES# low tRESW: Hold RES# low for the longer of:
20 tcyc
1.5 uS
All reset-related status registers are cleared
The RX can be placed into a reset state using the reset pin, named RES#.
Drive Reset low to reset the RX.
Reset must remain low for 20 ticks of the external bus clock or 1.5 uS, whichever is longer.
A pin reset clears all reset-related bits in the status registers.
In a few slides we’ll see the flowchart for reading these registers to determine the cause of a reset.
© 2011 Renesas Electronics America Inc. All rights reserved.

10. Voltage-Monitoring Reset
Internally generated by LVD
Caused by VCC < Vdet1 or VCC < Vdet2
Internal reset starts tdet (max 200uS) after VCC falls
Rising edge on VCC tVOFF (min 200uS) after falling edge
Power-on reset time (tPOR) of 20-50ms (35 typ.) starts after rising edge
RSTSR.LVDnF = 1 (n=1 or 2)
As we saw earlier in the slides on the LVD, the voltage detection circuit can also reset the RX. The LVD can be configured to generate a reset when the supply voltage drops below one of the LVD thresholds, Vdet1 or Vdet2.
The LVD reset starts shortly after the voltage drop, a maximum of 200 uS later. While the part can come out of reset if the supply rises again, the LVD holds it in reset for a minimum of 200 uS, shown in the diagram as tVOFF. This prevents the MCU from coming in and out of reset if the supply is bouncing around the threshold.
Once the voltage has risen and stabilized above the threshold, a Power On Reset delay, tPOR, is applied before the LVD releases the reset state.
Finally, flags in the Reset Status Register, shown on an earlier slide, are set appropriately.
© 2011 Renesas Electronics America Inc. All rights reserved.

11. Deep Software Standby Reset
Generated when deep software stdby exited by interrupt
Startup delay specified in DPSWCR.WTSTS[5:0]
RSTSR.DPSRSTF = 1
A select group of RX interrupt sources can be used to wake the chip up from Deep Software Standby Mode. When in Deep Software Standby Mode, these interrupts actually generate an internal reset rather than a normal interrupt sequence. During this reset, a startup delay specified in the Deep Standby Wait Control Register is in force. Once the reset state is exited, the DPSRSTF bit in the Reset Status Register is set.
© 2011 Renesas Electronics America Inc. All rights reserved.

12. Watchdog Resets Independent Watchdog (IWDT) Watchdog Timer (WDT)
Clock source = OCOCLK
IWDTSR.UNDFF indicates timeout/reset
Watchdog Timer (WDT)
Clock source = PCLK / divisor
RSTCSR.WOVF indicates timeout/reset
Also drives WDT# pin (do NOT connect to RST# pin!)
The RX includes two mechanisms for protecting against runaway code: The watchdog timer and the independent watchdog timer.
The independent watchdog timer, or IWDT, uses a dedicated 125 kHz on-chip oscillator as it’s source. It can be configured to generate interrupts or resets when it times out. When a reset is generated the underflow bit, UNDFF, in the Independent Watchdog Timer Status Register is set to a one.
Similarly, the watchdog timer can generate resets on time out conditions, too. The WDT has as its clock source the peripheral clock, or PCLK. The watchdog overflow bit, WOVF, in the Reset Control and Status Register is set when a reset is generated by the watchdog.
The Watchdog Timer also drivers the WDT# pin on the MCU low. This can be used to reset other circuitry on your board, but don’t connect it to the RST# pin on the RX – the reset signal is generated internally.
© 2011 Renesas Electronics America Inc. All rights reserved.

13. Determining Reset Source
In your startup code, follow this flowchart to determine the cause for a reset in the system. It’s important do check the various status bits in the order shown to properly determine the reset source.
The order is:
1) Watchdog timer,
2) Independent watchdog,
3) Deep software standby reset,
4) LVD resets starting with the higher, Vdet2, threshold,
5) Power-on resets.
If none of those sources where active, then your code can safely conclude that the reset was caused by the RES# pin being driven low.
© 2011 Renesas Electronics America Inc. All rights reserved.

14. Summary RX Voltage Detection Circuit (LVD)
LVD Control & Status Registers
RX Power-On Reset (POR)
Other RX Reset Sources
Determining Reset Source
Thank you!
In this module you’ve learned about :
-The RX Voltage Detection Circuit
-The registers that control the LVD
-The RX Power-On Reset circuit
-Other sources of Reset on the RX
-How software can determine the cause of a reset
Thanks for watching!
© 2011 Renesas Electronics America Inc. All rights reserved.

15. RX POR LVD Quiz

16. © 2011 Renesas Electronics America Inc. All rights reserved.
Thank You
Thank You
© 2011 Renesas Electronics America Inc. All rights reserved.