2. Hardware/Software Co-design Design of Hardware/Software Systems A Class Presentation for VLSI Course by : Akbar Sharifi Based on the work presented in : PROCEEDINGS OF THE IEEE 1997 GIOVANNI DE MICHELI, FELLOW IEEE RAJESH K.GUPTA, MEMBER, IEEE ------------------------------------------------------------------ Some Slides From : RASSP Education & Facilitation Program Module 14

3. Outline  Typical Co-Design Process  Components of HS Problems  Partitioning  Scheduling  Co-Simulation

4. Typical Co-design Process System Description (Functional) HW/SW Partitioning Software Synthesis Interface Synthesis Hardware Synthesis System Integration Concurrent processes Programming languages Unified representation (Data/control flow) Instruction set level HW/SW evaluation SWHW FSM- directed graphs Another HW/SW partition

5. Components of the Co-design Problem  Specification of the system  Hardware/Software Partitioning –Architectural assumptions - type of processor, interface style between hardware and software, etc. –Partitioning objectives - maximize speedup, latency requirements, minimize size, cost, etc. –Partitioning strategies - high level partitioning by hand, automated partitioning using various techniques, etc.  Scheduling –eration scheduling in hardware –operation scheduling in hardware –Instruction scheduling in compilers –Process scheduling in operating systems  Modeling the hardware/software system during the design process

6. Partitioning  A first order of impact on the cost/performance of the final design  In embedded systems : –Partition of system functionality into application-specific hardware and software executing on processors  In general purpose computing systems : –Captured by instruction set  In FPGAs : –Performing technology mapping

7. Scheduling   Hardware and software scheduling differ in formulation and overall goals   Assign an execution start time to each task in a set   Tasks linked by some relations (e.g. dependencies, priorities….)   Important when several modules in the partition share a single hw unit   Tasks execution requires the use of resources that can be limited in number   Serialization of some task execution

8. Operation Scheduling in Hardware  The techniques have been implemented in CAD tools  Operations are assumed to take a known, integer number of cycles to execute  Integer linear programming  The usual goal : minimize the overall execution latency  Satisfying the precedence and resource constraints   heuristic approaches: – – list scheduling, – –force directed scheduling

9. Scheduling  Instruction scheduling in hardware – –define a linear order of instructions – – instruction selection and register allocation – – goal: minimize code size and spills to memory   Coupling between scheduling – –Pipelined microprocessors – –Pipeline hazard avoidance   Process scheduling in operating systems – –SJF – –Roundrobin – –FIFO

10. Co-simulation  An HDL (VHDL or Verilog) simulation environment is used to perform behavioral simulation of the system hardware processes  A Software environment (C or C++) is used to develop the code  SW and HW execute as separate processes linked through UNIX IPC (interprocessor communications) mechanisms (sockets)

11. Verilog Co-simulation Example Verilog HW Simulator Module: Application specific hardware HW proc 1 HW proc 2 Module: Bus Interface Verilog PLI SW proc 1 SW proc 2 Software processes communicate with hardware simulator via UNIX sockets Verilog PLI (programming language interface) serves as translator, allowing hardware simulation models to communicate with software processes. UNIX sockets

12. VHDL Co-simulation Example VHDL Simulator Hardware Model in VHDL: VHDL Foreign Language Interface Software processes communicate with hardware simulator via foreign language interface Allowing hardware simulation models to “cosimulate” with software processes. SW proc 1 SW proc 2 RS232 module VME module

13. HHHHardware/Software co-design is the key design technology for digital systems

14. References  Hardware/Software Co-Design, 1996. (Codes/CASHE '96), Proceedings., Fourth International Workshop on  Hardware/Software Codesign of Embedded Systems, Design Modeling and Design Verification UCSD computer science professor Rajesh Gupta and Cal-(IT)² researcher Ingolf Krueger