1. Presenter: Jyun-Yan Li A hybrid approach to the test of cache memory controllers embedded in SoCs’ W. J. Perez, J. Velasco Universidad del Valle Grupo de Bionanoelectronica Cali, Colombia D. Ravotto, E. Sanchez, M. Sonza Reorda Dipartimento di Automatica e Informatica Torino, Italy 14 th IEEE International On-Line Testing Symposium 2008

2. Software-Based Self-Test (SBST) is increasingly used for testing processor cores embedded in SoCs, mainly because it allows at- speed, low-cost testing, while requiring limited (if any) hardware modifications to the original design. However, the method requires effective techniques for generating suitable test programs and for monitoring the results. In the case of processor core testing a particularly complex module to test is the cache controller, due to its limited accessibility and observability. In this paper we propose a hybrid methodology that exploits an Infrastructure Intellectual Property (I-IP) to complement an SBST algorithm for testing the data and instruction cache controller of embedded processors in SoCs. In particular, the I-IP may be programmed to monitor the system buses and generate the appropriate feedback about the correct result of the executed programs (in terms of obtained hit or miss operations). The effectiveness of the proposed methodology is evaluated resorting to a sample SoC design. 2

3. The testing cost is more and more high  How to generate effective test program in the SBST Some of case in [8] the timer could not be available or usable  Using timer to ensure cache hit or miss event 。 Assume the hit or miss max time 3

4. Modify cache structure to improve IDDQ testing [3] Modify cache structure to improve IDDQ testing [3] This paper Using March C- algorithm in the MBIST device [4] Using March C- algorithm in the MBIST device [4] Direct transformation of March-like test [5-7] Direct transformation of March-like test [5-7] Require special system for memory writing & reading when cache is disable 4 SBST strategy for data cache [8] SBST strategy for data cache [8] No require special Test cache Hardware based Software based enhance

5. Data cache algorithm Instruction cache algorithm Address calculation function  Marching 0: The unique bit is 0 in the tag bits  Marching 1: The unique bit is 1 in the tag bits 5

6. 6 start Calculate address (A) Write data (b) at A address Read data (Rx) at A address Rx=b? Nd*Nb times? Calculate address (A) Read data (Rx,b) at A address Write data (b) at A address Read data (Ry) at A address Rx⊕Ry=0? Nd*Nb times? No Yes error No error No Yes end Yes R hit W miss R miss R hit W hit

7. Purpose  access to every position of each cache block  Fully excite all circuits correlated with the tag, index and offset Address = As + a_tag + a_index + a_offset 7 D$ I$ Avoid overlapping, while cache fills tag consecutively

8. 8 Marching zero Marching one tag index offset Nt: number of bits required to address the cache block (as the tag bit) n: current data in the block m: current block in the cache Nt: number of bits required to address the cache block (as the tag bit) n: current data in the block m: current block in the cache 1 mod 5=1 (1+0) mod 4=1

9. The result address after calculating 9 n=0 m=0 n=0 m=1 n=1 m=0 n=2 m=0 n=4 m=0

10. 10 start Calculate address (A) Jump to A address Address A routine Jump to A address Nd*Nb times? Address A routine end Yes No R miss R hit Placed in cache non-cacheable for avoiding the loading in the cache of the respective machine code error exception

11. OpenRISC 1200 Result Line of codesizeRun timeFault coverage D-cache230410 byte159 Kcycle95% I-cache10,37029 Kbyte435 Kcycle95% 11 typeWrite policyGates Stuck-at fault D-cache8Kbyte direct mappedWrite through9854,528 I-cache8Kbyte direct mappedWrite through8313,805 Prevents the register to change some bit in the higher part of address without exception when memory exchange

12. A mixed methodology for testing the data and instruction cache control part A high stuck-at fault coverage with reduced cost My comment  No discuss about I-IP how to connect with processor  The ARM10 patterns have similar algorithm for data cache verification 12