1. IAY 0600 Digital Systems Design
VHDL discussion -1-
Signals and Data Types
Alexander Sudnitson
Tallinn University of Technology

2. Port Mode IN
Data comes in this port and can only be read within the entity. It can appear only on the right side of a signal or variable assignment. a
Entity
Port signal
Driver resides
outside the entity

3. Port Mode OUT
The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment
Entity
Port signal
Driver resides
inside the entity z
c <= z c
Output cannot be read within the entity

4. Port Mode OUT (with extra signal)
The value of an output port can only be updated within the entity. It cannot be read. It can only appear on the left side of a signal assignment.
Port signal
Entity
Driver resides
inside the entity x c z
z <= x
c <= x
Signal x can be
read inside the entity

5. Port Mode BUFFER Entity Port signal z c Port signal Z can be
Used for a signal that is an output from an entity. The value of the signal can be used inside the entity, which means that in an assignment statement the signal can appear on the left and right sides of the <= operator
The value read by the port is the same as the value driven by the port.
Entity
Port signal
Driver resides
inside the entity
Port signal Z can be
read inside the entity c z
c <= z

6. Port Mode INOUT Port signal Entity a Signal can be
The value of a bi-directional port can be read and updated within the entity model. It can appear on both sides of a signal assignment. The value read from the port is the result of resolution of the value assigned to the port and the values driven by all other sources that connect to the port.
Signal can be
read inside the entity
Entity
Port signal
Driver may reside both inside and outside of the entity a

7. Predefined types Predefined scalar types
Predifined (built-in) types are those defined in packges STANDARD and TEXTIO in the library STD.
Predefined types

8. Composite type
Array (groups elements of the same type together as single object). A one-demensional array is also called a vector.)
Record (may be of different type)

9. Fundamental parts of a Library
Library is a collection of commonly used pieces of code, grouped for reuse.
LIBRARY
PACKAGE 1
PACKAGE 2
TYPES
CONSTANTS
FUNCTIONS
PROCEDURES
COMPONENTS
TYPES
CONSTANTS
FUNCTIONS
PROCEDURES
COMPONENTS

10. VHDL for Synthesis (vs. for Simulation)
VHDL was originally developed as a language for describing digital systems for the purpose of documentation and simulation, but not for synthesis.
In 1999, the IEEE issued IEEE Std , IEEE Standard for VHDL Register Transfer Level (RTL) Synthesis. This standard described a subset of IEEE Std 1076 suitable for RTL synthesis. It also described the syntax and semantics of this subset with regard to synthesis.
IEEE defines a subset of the language that is considered the official synthesis subset.
A revision of this standard was issued in 2004.

11. Commonly Used Libraries
ieee
(Specifies multi-level logic system including STD_LOGIC, and STD_LOGIC_VECTOR data types)
std
(Specifies pre-defined data types (BIT, BOOLEAN, INTEGER, REAL, SIGNED, UNSIGNED, etc.), arithmetic operations, basic type conversion functions, basic text i/o functions, etc.)
work
(User-created designs after compilation)
Needs to be explicitly declared
Visible by default

12. Implicit context clause
LIBRARY std, work;
USE std.standard.all;

13. STD_ULOGIC (enumeration type)
Type STD_ULOGIC is declared inpackage STD_LOGIC_1164 as:
type_ulogic is ('U‘, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘L’, ‘H’, ‘-’);

14. STD_ULOGIC
Type STD_ULOGIC is unresolved type. By default, types whether predefined or user defined, are unresolved. It is illegal for two sources to drive the same signal (compiler error is generated).
Using STD_ULOGIC has an advantge that if our design unintenentionally creates two sourses for a signal (conflict), we can catch this error during compilation.

15. State and strength properties of std_ulogic
Value
Meaning
'U'
Uninitialized
‘X’
Forcing (Strong driven) Unknown
‘0’
Forcing (Strong driven) 0
‘1’
Forcing (Strong driven) 1
‘Z’
High Impedance
‘W’
Weak (Weakly driven) Unknown
‘L’
Weak (Weakly driven) 0. Models a pull down.
‘H’
Weak (Weakly driven) 1. Models a pull up.
‘-’
Don't Care

16. Syntax for signal, type, subtype declaration
Std_logic is a subtype of std_ulogic
subtype std_logic is resolved std_ulogic;
resolved is the name of a resolution function

17. Resolution table for std_logic
resolved function
uninitialized
unknown
forcing low
forcing high
high impedance
weak low
weak high
Don’t Care
weak unknown

18. STD_LOGIC versus STD_ULOGIC
STD_LOGIC is a type declared with a resolution function (defines, for all possible combinations of one or more sorce values, the resulting (resolved) value of a signal).
Example: a circuit with three-state outputs used in a bus interface; this is a situation where we intend for a signal to have multiple sources.
Std_logic is a subtype of Std_ulogic (but both consist of the same nine values) and is declared in package STD_LOGIC_1164 (there is defined resolution function with the name resolved.

19. STD_LOGIC versus STD_ULOGIC
A disadvantage of using std_logic instead of std_ulogic is that signals that are unintententionally multiply driven will not be detected as an error during compilation.
However, Standard IEEE Std 1164 recomends that std_logic be used instead of std_ulogic, even if a signal has only a single sourse (vendors have to optimize the simulation of models using unresolved types in accordance with Standard).

20. Our use of Std_logic values
We are interested in writing descriptions that will be synthesized and then implemented using FPGA (PLD).
In PLD/VHDL design methodology we will assign only the values ‘0’, ‘1’, or ‘–’ to std_logic signals. Sometimes we add ‘z’ to the previous list of values. Assigning values ‘H’ and ‘L’ to signals is not compatible with the device technology normally used in FPGAs (PLDs).
For testbenches we typically assign only the values ‘0’ and ‘1’ as inputs to the UUT.
During simulation we may observe the value ‘U’ and sometimes the value ‘X’. Since we will not assign values ‘H’ and ‘L’ to signals, we don’t expect to obseve the value ‘W’.

21. SIGNAL b : STD_LOGIC_VECTOR(7 downto 0);
Single Wire versus Bus
wire a
bus b 1 8
SIGNAL a : STD_LOGIC;
SIGNAL b : STD_LOGIC_VECTOR(7 downto 0);

22. STD_LOGIC_VECTOR type
type std_logic_vector is array
(natural range <>) of std_logic;

23. Standard Logic Vectors
SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL d: STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL e: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL f: STD_LOGIC_VECTOR(8 DOWNTO 0);
……….
a <= '1';
b <= "0000"; Binary base assumed by default
c <= B"0000"; Binary base explicitly specified
d <= "0110_0111"; -- You can use '_' to increase readability
e <= X"AF67"; Hexadecimal base
f <= O"723"; Octal base

24. Single versus Double Quote
Use single quote to hold a single bit signal
a <= '0', a <='Z‘
Use double quote to hold a multi-bit signal
b <= "00", b <= "11"

25. Vectors and Concatenation
SIGNAL a: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL b: STD_LOGIC_VECTOR(3 DOWNTO 0);
SIGNAL c, d, e: STD_LOGIC_VECTOR(7 DOWNTO 0);
a <= "0000";
b <= "1111";
c <= a & b; c = " "
d <= '0' & " "; d <= " "
e <= '0' & '0' & '0' & '0' & '1' & '1' &
'1' & '1'; -- e <= " "

26. The predefined type boolean
The predefined type boolean is defined as
type boolean is (false, true);
This type is used to represent condition values, which can control execution of a behavioral model. There are a number of operators that we can apply to values of different types to yield Boolean values, namely, the relational and logical operators. The relational operators equality (“=”) and inequality (“/=”) can be applied to operands of any type, provided both are of the same type.
For example, the expressions
123 = 123, 'A' = 'A', 7 ns = 7 ns
all yield the value true, and the expressions
123 = 456, 'A' = 'z', 7 ns = 2 us
yield the value false.

27. The predefined type boolean
To make an assignment of the value of one type to one of the others, the type of the value being assigned must be converted to the target type.
For example, if signal x is declared as type std_logic_vector and signal y is declared as type unsigned, and they are of equal length, each of the following assignments is illegal:
x <= y ; --illegal assignment, type conflict
y <= x ; --illegal assignment, type conflict
However, appropriate type conversions allow the following assignments to be made:
x <= std_logic_vector (y) ; -- valid assignment
y <= unsigned (x) ; -- valid assignment

28. Types UNSIGNED and SIGNED
Type std_logic is not defined as a numeric representation, no arithmetic operators are not defined for it in package STD_LOGIC_1164.
To avoid confusion separate types werw created for numeric representation in package NUMERIC_STD:
type unsigned is array (natural range <>) of std_logic;
type signed is array (natural range <>) of std_logic;
Type signed is interpreted as a signed binary number in 2´s complement form. The leftmost element is the sign bit.

29. Context clause to use unsigned and signed
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;

30. Conversion between Std_logic_vector, Unsigned and Signed
This conversion is easy to accomplish because these are considered clsely related. Type conversion between closely related types is accomplished by simply using the name of target type as it were a function.
For example, if x is std_logic_vector and y is unsigned, and they are ofequal length, than asigments
x <= y; and y <= x;
are illegal.
Type conversions are allowed assignments to be made:
x <= std_logic_vector (y);
y <= unsigned (x);

31. Functions to convert between types
signed and signed and integer
Examples:
y <= to_unsigned (i, 8);
x <= std_logic_vector (to_unsigned (i, 8));

32. Simplified syntax of package declaration
Package is a primary design unit used to organize and collect together related commonly used declarations (constants,types, functions, procedures).

33. Simplified syntax of package body

34. Functions to convert between types

35. Port types for synthesis
A synthesizer must translate all types used for signals into types that can represent wires. Typically, a synthesizer converts all types to either std_logic or std_logic_vector.

36. Type translations made by a synthesizer

37. VHDL operators are listed from higher to lower precedence
a = floor_div(a, n) * n + (a mod n)
a = (a / n) * n + (a rem n)
9 mod 5 = rem 5 = 4
9 mod (-5) = rem (-5) = 4
(-9) mod 5 = (-9) rem 5 = -4
(-9) mod (-5) = (-9) rem (-5) = -4

38. Shift operators Shift operators. Let A = “10010101”
A sll 2 = “ ” --shift left logical, filled with ‘0’
A srl 3 = “ ” --shift right logical, filled with ‘0’
A sla 3 = “ ” --shift left arithmetic, filled with right bit
A sra 2 = “ ” --shift right arithmetic, filled with left bit
A rol 3 = “ ” --rotate left by 3
A ror 5 = “ ” --rotate right by 5