1. FPGA Implementation of Denoising in OFDM Systems using DSP Design Module Prof. Brian L. Evans PhD Students Jing Lin, Marcel Nassar & Karl Nieman Wireless Networking and Communications Group Department of Electrical and Computer Engineering Cockrell School of Engineering The University of Texas at Austin January 18, 2012

2. Outline Smart power grids Powerline noise Cyclostationary Gaussian mixture Noise Mitigation Feedback for NI Q&A/Ideas for Current Semester 1 ISTOCKPHOTO.COM/© SIGAL SUHLER MORAN IEEE Signal Processing Magazine Special Issue on Signal Processing Techniques for the Smart Grid, September 2012. Background | System Design and Implementation | Feedback for NI | Q&A

3. Smart Grid Central power plant Wind farm Houses Offices HV-MV Transformer Industrial plant Utility control center Integrating distributed energy resources Smart meters Automated control for smart appliances Grid status monitoring Device-specific billing 2 High Voltage (HV) 33 kV – 765 kV Medium Voltage (MV) 1 kV – 33 kV Background | System Design and Implementation | Feedback for NI | Q&A

4. Local utility MV-LV transformer Smart meters Data concentrator Smart Grid Communications Home area data networks connect appliances, EV charger and smart meter via powerline or wireless links Smart meter communications between smart meters and data concentrator via powerline or wireless links Communication backhaul carries traffic between concentrator and utility on wired or wireless links 3 Low voltage (LV) under 1 kV Background | System Design and Implementation | Feedback for NI | Q&A

5. Use orthogonal frequency division multiplexing (OFDM) Communication challenges oCoChannel distortion oNoNon-Gaussian noise Powerline Communications (PLC) CategoriesBandBit RatesCoverageEnablesStandards Narrowband 3-500 kHz ~500 kbps Multi- kilometer Smart meter communication (ITU) PRIME, G3 ITU-T G.hnem IEEE P1901.2 Broadband 1.8-250 MHz ~200 Mbps <1500 m Home area data networks HomePlug ITU-T G.hn IEEE P1901 4 Background | System Design and Implementation | Feedback for NI | Q&A

6. Impulsive Noise in PLC 5 Outdoor medium-voltage line (St. Louis, MO) Cyclostationary noise becomes impulsive after interleaving Interleave Indoor low-voltage line (UT Campus) Background | System Design and Implementation | Feedback for NI | Q&A

7. Impulsive Noise in OFDM Systems FFT spreads received impulsive noise across all FFT bins SNR of each FFT bin is decreased Receiver communication performance degrades 6 IFFTFilter + FFT Equalizer and detector Vector of symbol amplitudes (complex) Channel Receiver x y Gaussian (w) + Impulsive Noise (e) Background | System Design and Implementation | Feedback for NI | Q&A

8. Impulsive Noise Mitigation (Denoising) N FFT bins (tones) Transmitter null tones have zero power Received null tones contain noise Impulsive noise estimation Exploit sparse structure of null tones F J is over complete dictionary e is sparse vector g is complex Gaussian (g = F w) 7 IFFTFilter ++ FFT Equalizer and detector Impulsive noise estimation Gaussian (w) + Impulsive Noise (e) Vector of symbol amplitudes (complex) + - Channel Receiver J is set of null tones (i.e. x j = 0) F is N x N FFT matrix x y |J| x N Background | System Design and Implementation | Feedback for NI | Q&A

9. Approximate Message Passing (AMP) M = number of null tones N = FFT size 8 Background | System Design and Implementation | Feedback for NI | Q&A

10. FPGA Hardware Design via NI DSP Design Module DSP Diagram implements FFT and IFFT (N = 256) accumulators, adders, subtracters, multipliers, dividers 2-norm calculation (squaring + accumulating) stream interleave/de-interleave, computational parallelism exponential function using Taylor series approximation 9 Background | System Design and Implementation | Feedback for NI | Q&A

11. Test System for G3-PLC Using FPGA 127 199.2 data 0000 tone f (kHz) 23 35.94 58 90.63 tone map: PXIe-7965R (Virtex 5) PXIe-1082 Real-time host 10 Background | System Design and Implementation | Feedback for NI | Q&A

12. FPGA Timing/Resource Utilization Base logic clock = 40 MHz, most data streams 16 bits wide Execution time: 5 iterations × 4776 cycles/iteration = 23880 cycles Supports streaming operation at 400 kS/s (G3 sample rate) Can recover up to 8 dB SNR in impulsive noise environments 100x reduction in avg bit-error-rate for test system using QPSK, 40 dB impulse at p = 0.03: Preliminary resource utilization: Possible to exploit more parallelism for higher throughput with AMPwithout AMP 11 Background | System Design and Implementation | Feedback for NI | Q&A (full AMP, num_iterations = 5)

13. Feedback for NI (DSP Design Module) Aesthetics Support local variables Reduce DSP subdiagram overhead Improve transparency of FFT/IFFT Coregen interface – e.g. adjusting throughput substantially affects ET Better feedback from compiler -- I never saw any overmapping errors but had lots of hangs and had to manually cancel Bit manipulation should not cost ET Identify “slowest path” visually to help designers reduce ET and optimize algorithm timing Easy parallelization – e.g. implement simple interface to fork stream operations into parallel blocks 12 Background | System Design and Implementation | Feedback for NI | Q&A

14. Feedback for NI (LabVIEW) Complex FXP FXP FFT and exp Improve FXP array support Operations like vector sum, convert to FXP should be supported Remove discrepencies between LV FXP and DSP Diagram FXP “adapt to input” auto-sizings 13 Background | System Design and Implementation | Feedback for NI | Q&A

15. Plan for Spring 2013 Jan: Finish AMP implementation Upload project to Brian’s website to spotlight DSP Designer Feb: Use P2P to implement OFDM link w/ third FlexRIO (note: need another FlexRIO) March-April: Demonstrate link over two physical channels G3 powerline testbed Recorded/synthesized noise playback Live powerline noise 802.15.4g or 802.11ah at 2.4 GHz using Ettus boards (Note: Mike still has one of our interposer boards) 14 Background | System Design and Implementation | Feedback for NI | Q&A