1. General Purposes Input/ Output Daughter board for Univ Eval Rev B Julien Cercillieux University of Hawaii juliend@hawaii.edu

2. Purpose of design Expanding simplification of using the Universal Evaluation Board designing circuits. To simplify the testing of component by quickly checking the functionality using test signal.

3. Physical Dimension of PCB Design 4'' x 4 '' 4 layers  2 trace/pads planes  ground plane and power plane Trace and trace clearance width 8- 10 mils ~30 FPGA GPIO pads 12 ADC Channel pads 3 ADC SMA input 4 DACs' SMA output

4. Power planes The are 3 split power planes. Green - 3.3v Purple - 2.5v Yellow - 5.0v. Copper Clearance – 10 mils

5. On-board PCB Packages 4 DAC – MCP4921  12 bit w/ 8 pads  Vdd – 3.3v, Vref - 2.5V  Load Input Current – Vdd.5mA  SPI interface 1 ADC – ADS7953  16 channel muxs 12 bit ADC  SPI interface  Vref – 2.5V VA - 3.3, VBD – 3.3 V  Supply Current –VA- 1 mA  VBD – 1.8 mA

6. Buffer Amplifier – BUF04701  Rail Set to 0-5v 3.3V Linear Voltage Regulator – AP7333  Max Load – 300mA  V_input Range - 2- 6v 2.5V Voltage Regulator – ADP3338  Max Load – 2 A  V_input Range – 2.7 – 8v

7. Placement of Component The 4 DACs' and 1 ADC are sandwiched between the 2 80 pin connectors The Buffer Amp are closer to the 4 DACs' SMA output All the DAC, ADC and buffer amp are located on the top layers. Most of the Capacitors are located bottom layers along with 80 pinn connectors.

8. DFM Design Result Plated hole to copper spacing of 8.4 mils on layer 2copper.G2L, at X=3.2874", Y=2.38559". Plated hole to copper spacing of 8.4 mils on layer 2copper.G2L, at X=3.2874", Y=3.81559". Plated hole to copper spacing of 8.4 mils on layer 2copper.G2L, at X=4.7126", Y=3.81559". Plated hole to copper spacing of 8.4 mils on layer 2copper.G2L, at X=4.7126", Y=2.38559". https://www.freedfm.com/freedfm/0020887503666700/ results/summary2.htm

9. http://www.my4pcb.com/net35/FreeDFMNet/FDFMViewer.aspx https://www.my4pcb.com/Net35/quote/quote_code.aspx?ACTION=RECALL&QID=366 6700&CID=208875