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H IGH S PEED, P LUGGABLE O PTICAL B ACKPLANE C ONNECTOR T ECHNOLOGY Richard Pitwon, Ken Hopkins, Dave Milward Xyratex Technology Ltd International Symposium.

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Presentation on theme: "H IGH S PEED, P LUGGABLE O PTICAL B ACKPLANE C ONNECTOR T ECHNOLOGY Richard Pitwon, Ken Hopkins, Dave Milward Xyratex Technology Ltd International Symposium."— Presentation transcript:

1 H IGH S PEED, P LUGGABLE O PTICAL B ACKPLANE C ONNECTOR T ECHNOLOGY Richard Pitwon, Ken Hopkins, Dave Milward Xyratex Technology Ltd International Symposium on Photonic Packaging Electrical Optical Circuit Board and Optical Backplane organized by Fraunhofer IZM & VDI/VDE-IT Munich, Germany November 2006 David R. Selviah, Ioannis Papakonstantinou Kai Wang, F. Anibal Fernández University College London (UCL)

2 Purpose British government funded initiative to investigate incorporation of optical backplanes into high bandwidth systems and develop solutions T HE S TORLITE P ROJECT 2 ISPP Electro-Optical Circuit Board | Munich 2006 University College London Investigation into performance enabling polymer waveguide structures and characterisation Xyratex Investigation into optical backplane connector technology and prototype solution development Exxelis Ltd Optical PCB manufacture Duration June 2003 – November 2005

3 R ESEARCH O BJECTIVES Investigation of current state of the art in optical PCB technology research Polymeric waveguide fabrication and characterisation Optical PCB Design Rules Investigation into low-cost technology drivers Method of pluggable daughtercard connection to an optical backplane Development of prototype solutions Parallel optical transceiver and pluggable optical backplane connector Development of prototype demonstration assembly 3 ISPP Electro-Optical Circuit Board | Munich 2006

4 R ESEARCH AND D EVELOPMENT O VERVIEW High speed parallel optical transceiver Opto-mechanical registration interface Low-cost optical backplane connection mechanism Low cost precision optical alignment and assembly method Optical PCB interface coupling method Prototype demonstration unit 4 ISPP Electro-Optical Circuit Board | Munich 2006

5 H IGH B ANDWIDTH B ACKPLANE E NVIRONMENTS 48 Drive RAID Storage System 12 Drive SBOD Storage System 16 Drive EBOD Storage System 5 ISPP Electro-Optical Circuit Board | Munich 2006

6 H IGH B ANDWIDTH B ACKPLANE Power Module Multi Layer Interconnect Backplane Controller Module Dual Port Disk Drives Air Flow Channels High Speed Connectors To Controllers 6 ISPP Electro-Optical Circuit Board | Munich 2006

7 B ACKPLANE E NGAGEMENT M ODEL Orthogonal daughtercard engagement to backplane Embedded optical channels to carry high speed serial signals between cards Copper layers to carry power, control signals and low speed signals High bandwidth backplane 7 ISPP Electro-Optical Circuit Board | Munich 2006

8 Daughtercard VCSEL P ROPOSED C OUPLING P RINCIPLE Optical Waveguides Backplane Surface emitting photonics used on daughtercard interface Butt-coupling scheme allows for minimum number of intermediary optical interfaces Copper Planes Copper Traces 8 ISPP Electro-Optical Circuit Board | Munich 2006

9 P ARALLEL O PTICAL T RANSCEIVER D ESIGN Quad duplex parallel optical transceiver 10.3 Gbps per channel (82 Gb/s aggregate bandwidth) Electronic daughtercard connector Flexible and rigid PCB sections Optical backplane interface Flexible mid-section Rigid base section Rigid optical interface Electronic connector Active opto-mechanical coupling interface 9 ISPP Electro-Optical Circuit Board | Munich 2006

10 P HOTONIC I NTERFACE D ESIGN Source: ULM Photonics GmbH Source: Microsemi Corporation Source: GRINTech GmbH VCSEL Array PIN Array GRIN Lens Array MT compatible interface 10 ISPP Electro-Optical Circuit Board | Munich 2006

11 O PTOELECTRONIC PCB WITH MT – S OCKET I NTERPOSER 11 ISPP Electro-Optical Circuit Board | Munich 2006 (a) (b) MT-socket interposer MT-plug Ceramic lens holder MT-pins

12 MT - S OCKET I NTERPOSER ON THE T OP OF B ACKPLANE 12 ISPP Electro-Optical Circuit Board | Munich 2006 3.8870 ± 0.0001 0.35650 ± 0.00001 0.66 ± 0.01 0.02 mm 0.53125 mm 3.8825 ± 0.005 mm 0.25 mm

13 A CTUAL A LIGNMENT OF THE C OMPONENT 13 ISPP Electro-Optical Circuit Board | Munich 2006 waveguides registration features 3886 µm

14 S UPPORT D AUGHTERCARD D ESIGN 4 XFP ports PCB material Rogers 4350 on outer layers Transceiver receptacle 4 Port 10 GbE LAN Physical Relay board Host interface 14 ISPP Electro-Optical Circuit Board | Munich 2006

15 C HARACTERISATION S ETUP MT patchcord for stand alone testing Physical layer relay board Test traffic: 10 GbE LAN (10.3 Gbps) VCSEL bias current: 11.91 mA VCSEL modulation current: 9.8 mA Divergence: 25° Output optical power: 0.43 mW Average optical jitter: 31.2 ps (Pk – Pk) 15 ISPP Electro-Optical Circuit Board | Munich 2006

16 C ONNECTOR M ECHANISM Principal Function Elevation and retraction of optical interface 16 ISPP Electro-Optical Circuit Board | Munich 2006

17 A LIGNMENT M ETHOD B ASED ON MT C ONCEPT 17 ISPP Electro-Optical Circuit Board | Munich 2006 daughtercard MT-pin 4 VCSEL array MT-pin 4 PD array x z y θ φ backplanearray of 12waveguides MT-holes

18 P OLYMER O PTICAL W AVEGUIDE T ECHNOLOGY 18 ISPP Electro-Optical Circuit Board | Munich 2006

19 P OLYMER W AVEGUIDE C HARACTERISTICS Waveguide Material UV-curable polymeric acrylate (Truemode®) Propagation loss @ 850 nm: 0.04 dB/cm Heat degradation resilience:up to 350°C Waveguide properties Size: 70 µm x 70 µm Core index: 1.556 Cladding index: 1.526 Numerical aperture:0.302 Waveguide Array Centre to centre pitch: 250 µm 19 ISPP Electro-Optical Circuit Board | Munich 2006

20 P ROTOTYPE D EMONSTRATOR C ONSTRUCTION Separate passive electrical backplane Passive Electrical Backplane 20 ISPP Electro-Optical Circuit Board | Munich 2006

21 Daughtercard Guide Features P ROTOTYPE D EMONSTRATOR C ONSTRUCTION 21 ISPP Electro-Optical Circuit Board | Munich 2006

22 Daughtercard Power Supply P ROTOTYPE D EMONSTRATOR C ONSTRUCTION 22 ISPP Electro-Optical Circuit Board | Munich 2006

23 Daughtercard to Optical Backplane Coupling Evaluation P ROTOTYPE D EMONSTRATOR C ONSTRUCTION 23 ISPP Electro-Optical Circuit Board | Munich 2006

24 Optical Backplane Integration Separate optical PCB P ROTOTYPE D EMONSTRATOR C ONSTRUCTION 24 ISPP Electro-Optical Circuit Board | Munich 2006

25 Complete Demonstration Unit P ROTOTYPE D EMONSTRATOR C ONSTRUCTION 25 ISPP Electro-Optical Circuit Board | Munich 2006

26 T EST AND C HARACTERISATION Optical Coupling Characterisation Test traffic: 10 GbE LAN (10.3 Gbps) Wavelength: 850 nm Reference Signal – No Waveguide Jitter:0.34 UI Relative Loss:0 dB 10 cm Waveguide with Isapropanol Jitter0.36 UI Relative Loss4.5 dB 10 cm Waveguide – Diced and Polished Jitter0.56 UI Relative Loss6.9 dB 10 cm Waveguide – Diced Only Jitter0.89 UI Relative Loss7.9 dB Arrangement: Active connector – waveguide - patchcord Multimode MT fibre patchcord Active prototype connector 26 ISPP Electro-Optical Circuit Board | Munich 2006

27 T EST AND C HARACTERISATION Arrangement: Test traffic source (10 GbE LAN) Fibre cable XFP Port 1 (Rx) Daughtercard 1 Connector 1 (Tx) Optical PCB Connector 2 (Rx) Daughtercard 2 XFP Port 2 (Tx) Fibre cable Traffic Capture High Speed Network Link Evaluation Bit Error Rate < 10 -12 27 ISPP Electro-Optical Circuit Board | Munich 2006

28 C ONTOUR M AP OF VCSEL A ND PD M ISALIGNMENT 28 ISPP Electro-Optical Circuit Board | Munich 2006 (a) Contour map of relative insertion loss compared to the maximum coupling position for VCSEL misalignment at z = 0. (b) Same for PD misalignment at z = 0. Resolution step was Δx = Δy = 1 µm. Dashed rectangle in the middle of the maps corresponds to the expected relative insertion loss according to the calculated misalignments along x and y in text slides. The minimum insertion loss was 4.4 dB, corresponded to x = 0, y = 0, z = 0

29 T OLERANCES A LONG X, Y A ND Z FOR C ONNECTOR C OMPONENTS 29 ISPP Electro-Optical Circuit Board | Munich 2006 XyZ MT-plug 3 μm (pin-to-pin) 3 μm (pin-to-GRIN)________ MT-socket 3 μm (hole-to-hole) 3 μm (hole-to-waveguide)________ OPCB features +2.5 μm (increase in registration wall-to-wall spacing due to overexposure) 2.5 μm (due to 5 μm extra spacing between feet of interposer) 1 μm (core thickness control) +10 μm (accuracy of dicing in respect to the dicing lines on the board) +2.5 μm (backstop shift due to overetching) Tolerance of MT interposer socket to waveguides 8 μm or 3 μm if overexposure widening is known and reproducible 4 μm +12.5 μm or +10 μm if overexposure widening is known and reproducible Combined tolerance of VCSEL and PIN to waveguides 11 μm or 6 μm if overexposure widening is known and reproducible 7 μm +12.5 μm or +10 μm if overexposure widening is known and reproducible

30 R ELATIVE I NSERTION L OSS OF VCSEL A ND PD A S T HEY M OVE A WAY F ROM THE OPCB W AVEGUIDES. 30 ISPP Electro-Optical Circuit Board | Munich 2006 VCSEL Photo Detector

31 C ROSSTALK M EASUREMENT 1 31 ISPP Electro-Optical Circuit Board | Munich 2006 Power received at the end of 0th waveguide as a function of the lateral distance of the VCSEL from its center. The boundaries and the centers of the waveguides on the backplane are marked. In the cladding power drops at a rate of 0.011 dB/µm

32 32 ISPP Electro-Optical Circuit Board | Munich 2006 Signal-to-cross-talk (SCR) levels that 0th waveguide experiences from its adjacent waveguides. C ROSSTALK M EASUREMENT 2

33 33 ISPP Electro-Optical Circuit Board | Munich 2006 SCR experienced by waveguides number 1 and 4 and of waveguides number 2 and 3 from the array of four in the connector if all are in use. Dashed-dot lines determine the boundaries of the maximum expected cross-talk based on current connector tolerances. C ROSSTALK M EASUREMENT 3

34 S TABILITY T ESTING OF THE MT – S OCKET I NTERPOSER 1 34 ISPP Electro-Optical Circuit Board | Munich 2006 Insertion loss and signal to cross-talk (SCR) as a function of mating cycle for 75 engagements.

35 35 ISPP Electro-Optical Circuit Board | Munich 2006 Histogram of insertion loss S TABILITY T ESTING OF THE MT – S OCKET I NTERPOSER 2

36 Purpose Industrial collaborative effort to develop commercial technology drivers for optical backplane and connector technology and drive the proliferation of optical backplane technology into the industrial sector T HE C ANDEO P ROJECT 36 ISPP Electro-Optical Circuit Board | Munich 2006 Xyratex Commercial development of proprietary parallel optical transceiver technology Samtec Commercial development of optical backplane engagement mechanism

37 C ANDEO C URRENT S TATUS High speed parallel optical transceiver design modified for commercial design Single stage optical backplane engagement mechanism developed Commercial form factor module designed and developed First mechanical prototype on exhibition by Samtec and Xyratex at Electronica 2006, Samtec booth 419 in Hall B4 37 ISPP Electro-Optical Circuit Board | Munich 2006 Phase I (currently underway) Phase I (currently underway)

38 I NTEGRATED O PTICAL AND E LECTRONIC PCB M ANUFACTURING 38 ISPP Electro-Optical Circuit Board | Munich 2006 Academic Partners University College London (UCL) – Waveguide design, modelling, measurement Heriot-Watt University – Direct UV laser waveguide fabrication Loughborough University – Laser ablation, surface treatment, printing waveguide fabrication, flip-chip assembly Industrial Partners Xyratex – End user and project manager BAE Systems – End user Renishaw – End user Exxelis – Polymer chemistry, lithographic waveguide fabrication Cadence – PCB layout tools Rsoft Design – Optical modeling tools Xaar – print head technology Purpose To compare multimode, polymer waveguide manufacture techniques for large area optical backplanes and to develop design rules.

39 S UMMARY Xyratex White Papers An Optical Backplane Connection System with Pluggable Active Board Interfaces An Optical Backplane Connection System with Pluggable Active Board Interfaces (available from Xyratex website) Pluggable Optical Backplane Connector Technology (available) Pluggable Optical Backplane Connector Technology (available) Optical vs Copper Cost and Performance Evaluation (pending) Optical vs Copper Cost and Performance Evaluation (pending) www.xyratex.com Xyratex White Papers An Optical Backplane Connection System with Pluggable Active Board Interfaces An Optical Backplane Connection System with Pluggable Active Board Interfaces (available from Xyratex website) Pluggable Optical Backplane Connector Technology (available) Pluggable Optical Backplane Connector Technology (available) Optical vs Copper Cost and Performance Evaluation (pending) Optical vs Copper Cost and Performance Evaluation (pending) www.xyratex.com Intellectual Property 7 patent applications related to optical PCB interconnect and communication structures and methodologies Intellectual Property 7 patent applications related to optical PCB interconnect and communication structures and methodologies 39 ISPP Electro-Optical Circuit Board | Munich 2006

40 S UMMARY UCL Publications (available from UCL website) Papers published on waveguide devices Sources misalignment x, y, z Detector misalignment x, y, z Straight tapered waveguide Bends Propagation loss Thermal optics switch Power splitter Precision low cost alignment www.ee.ucl.ac.uk/%7Eodevices/ UCL Publications (available from UCL website) Papers published on waveguide devices Sources misalignment x, y, z Detector misalignment x, y, z Straight tapered waveguide Bends Propagation loss Thermal optics switch Power splitter Precision low cost alignment www.ee.ucl.ac.uk/%7Eodevices/ 40 ISPP Electro-Optical Circuit Board | Munich 2006

41 Thank You for Your Attention Richard C A Pitwon Senior Photonics Engineer Ken Hopkins Hardware Architect Dave Milward Development Manager E-mail: rpitwon@xyratex.com 41 ISPP Electro-Optical Circuit Board | Munich 2006 David R Selviah F. Anibal Fernández Senior Academics Ioannis Papakonstantinou Postgraduate Researcher Kai Wang Research Fellow E-mail: d.selviah@ee.ucl.ac.uk Acknowledgements UK Department of Trade and Industry EPSRC Exxelis Dr Navin Suyal Prof. Frank Tooley


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