1. C HAPTER F IVE S YNCHRONOUS S EQUENTIAL L OGIC 1

2. 2 It consists of a combinational circuit to which storage elements are connected to form a feedback path. The storage elements are devices capable of storing binary information. The binary information stored in these elements at any given time defines the state of the sequential circuit at that time.

3. 3 S EQUENTIAL C IRCUITS Combinational Circuit Memory Elements Inputs Outputs Synchronous Combinational Circuit Flip-flops Inputs Outputs Clock

4. The outputs in a sequential circuit are a function not only of the external inputs, but also of the present state of the storage elements. The next state of the storage elements is also a function of external inputs and the present state. The behavior of an asynchronous sequential circuit depends upon the input signals at any instant of time and the order in which the inputs change. A synchronous sequential circuit (clocked sequential circuit) is a system whose behavior can be defined from the knowledge of its signals at discrete instants of time. 4

5. Synchronization is achieved by a timing device called a clock generator, which provides a clock signal having the form of a periodic train of clock pulses. The clock signal is commonly denoted by the clk. The clock pulses determine when computational activity will occur within the circuit, and other signals (external inputs) determine what changes will take place affecting the storage elements and the outputs. 5

6. Storage elements that operate with signal levels (rather than signal transitions) are referred to as latches. Those controlled by a clock transition are flip-flops. Latches are said to be level sensitive devices. Flip-flops are edge-sensitive devices. 6

7. L ATCHES SR Latch (cross coupled NOR) S R Q 0 QQ’ 0 0 0 0 1 0 0 01 Q = Q 0 Initial Value 7

8. L ATCHES SR Latch S R Q 0 Q Q’ 0 0 001 0 0 1 1 0 0 0 10Q = Q 0 8

9. L ATCHES SR Latch S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 00 0 1 1 0 1 Q = 0 Q = Q 0 9

10. L ATCHES SR Latch S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 1 1 0 1 0 01 Q = 0 Q = Q 0 Q = 0 10

11. L ATCHES SR Latch S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 101 1 0 0 0 1 0 1 10 Q = 0 Q = Q 0 Q = 1 11

12. L ATCHES SR Latch S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 101 1 0 010 1 0 1 1 0 0 1 10 Q = 0 Q = Q 0 Q = 1 12

13. L ATCHES SR Latch S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 101 1 0 010 1 0 110 1 1 0 0 1 1 1 00 Q = 0 Q = Q 0 Q = 1 Q = Q’ 0 13

14. L ATCHES SR Latch S R Q 0 Q Q’ 0 0 001 0 0 110 0 1 001 0 1 101 1 0 010 1 0 110 1 1 000 1 1 1 1 0 1 1 00 Q = 0 Q = Q 0 Q = 1 Q = Q’ 0 14

15. L ATCHES SR Latch S RQ 0 Q0Q0 0 10 1 01 1 Q = Q’=0 No change Reset Set Invalid S R Q 0 Q = Q’=1 0 11 1 00 1 Q0Q0 Invalid Set Reset No change 15

16. 16

17. C ONTROLLED L ATCHES SR Latch with Control Input (operates with signal level) En S RQ 0 x x Q0Q0 1 0 0 Q0Q0 1 0 10 1 1 01 1 1 1Q = Q’ No change Reset Set Invalid 17

18. C ONTROLLED L ATCHES D Latch (Transparent Latch) C=En D (data)Q 0 x Q0Q0 1 00 1 11 No change Reset Set C Timing Diagram D Q t Output may change 18

19. C ONTROLLED L ATCHES D Latch ( D = Data ) C DQ 0 x Q0Q0 1 00 1 1 No change Reset Set C Timing Diagram D Q Output may change 19

20. 20

21. 21 When latches are used for the storage elements, a serious difficulty arises. The state transitions of the latches start as soon as the clock pulse changes to the logic-1 level. F LIP -F LOPS

22. If the inputs applied to the latches change while the clock pulse is still at the logic-1 level, the latches will respond to new values and a new output state may occur. The new state of a latch appears at the output while the pulse is still active. This output is connected to the inputs of the latches through the combinational circuit. The result is an unpredictable situation, since the state of the latches may keep changing for as long as the clock pulse stays at the active level. 22

23. Controlled latches are level-triggered Flip-Flops are edge-triggered It operates with signal transitions C CLKPositive Edge CLKNegative Edge 23

24. F LIP -F LOPS Master-Slave D Flip-Flop D Latch (Master) DCDC Q D Latch (Slave) DCDC QQD CLK D Q Master Q Slave Looks like it is negative edge-triggered MasterSlave 24

25. F LIP -F LOPS Edge-Triggered D Flip-Flop DQ Q DQ Q Positive Edge Negative Edge 25 Q(t+1) = D

26. F LIP -F LOP C HARACTERISTIC E QUATIONS Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) 0000 0011 010 011 100 101 110 111 No change Reset Set Toggle 26

27. F LIP -F LOP C HARACTERISTIC E QUATIONS Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) 0000 0011 0100 0110 100 101 110 111 No change Reset Set Toggle 27

28. F LIP -F LOP C HARACTERISTIC E QUATIONS Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) 0000 0011 0100 0110 1001 1011 110 111 No change Reset Set Toggle 28

29. F LIP -F LOP C HARACTERISTIC E QUATIONS Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) 0000 0011 0100 0110 1001 1011 1101 1110 No change Reset Set Toggle 29

30. F LIP -F LOP C HARACTERISTIC E QUATIONS Analysis / Derivation JQ QK JKQ(t)Q(t)Q(t+1) 0000 0011 0100 0110 1001 1011 1101 1110 K 0100 J1101 Q Q(t+1) = JQ’ + K’Q 30

31. F LIP -F LOPS JK Flip-Flop JQ QK D = JQ’ + K’Q 31

32. F LIP -F LOPS T (toggle) Flip-Flop D = TQ’ + T’Q = T  Q JQ QK T DQ Q T D = JQ’ + K’Q TQ Q 32

33. F LIP -F LOP C HARACTERISTIC T ABLES DQ Q DQ(t+1) 00 11 Reset Set JKQ(t+1) 00Q(t)Q(t) 010 101 11Q’(t) No change Reset Set Toggle JQ QK TQ Q TQ(t+1) 0Q(t)Q(t) 1Q’(t) No change Toggle 33

34. F LIP -F LOPS WITH D IRECT I NPUTS Asynchronous Reset DQ Q R Reset RDCLKQ(t+1) 0xx0 34

35. F LIP -F LOPS WITH D IRECT I NPUTS Asynchronous Reset DQ Q R Reset RDCLKQ(t+1) 0xx0 10 ↑ 0 11 ↑ 1 35