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Basic digital logic J. Christiansen, CERN - EP/MIC

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2 Basic digital logic J. Christiansen, CERN - EP/MIC Jorgen.Christiansen@cern.ch

3 December 2003J.Christiansen/CERN2 General digital functions Any digital function can be made from this structure Logic: Logical operations –And, Or, Additions, Multiplications, Divisions, etc. Memory: Storage of variables and state –Latch, Flip-Flops, registers, register files, SRAM, DRAM, ROM, etc. Mixed signal design: Both digital and analog functions on same IC / board LogicMemory ADCDAC Analog

4 December 2003J.Christiansen/CERN3 Logic Logic built from basic building blocks: Gates NameFunctionTruth tableSymbol And Others: Nand, Nor, Exclusive or, Multiplexer, Tristate, Full adder, Buffers, etc. a x b a b 0 1 01 0 01 0 Ora + b a b 0 1 01 0 11 1 Inversiona a 0 1 1 0 a b a b a

5 December 2003J.Christiansen/CERN4 Memory elements Storage of a logic value for a give time period D L Q Latch 1 1 Q 0 1 D L 0 1 X0Q Flip-Flop Q 0 1 DC 0 1 XQ Level sensitive Edge sensitive Clock DQ D L QD L Q Master – slave latch Memory array Decoding Address Rd/wr Data Memories RAM: Random Access Memory SRAM:Static RAM DRAM: Dynamic RAM FLASH: “Permanent” RAM (no power needed) ROM: Read Only Memory PROM: Programmable ROM EPROM: Erasable PROM (with UV light) EEPROM: Electrical Erasable PROM DPM:Dual Port Memory FIFO:First In - First Out Address decoding normally divided in row and collumn decoding

6 December 2003J.Christiansen/CERN5 Logic optimization Reduction of logical expressions : (~ = inversion) –a x (b x c) = (a x b) x c = abc; a + (b + c) = (a + b) + c = a+b+c –a + ~a = 1; a x ~a = 0 –a x (b + c) = ab + ac; a + (b x c) = a + bc (no reduction) –~(a + b) = ~a x ~b; ~(a x b) = ~a + ~b Eg. ~a~b~c~d + ~ab~c~d = ~a~c~d x ( ~b + b ) = ~a~c~d x ( 1 ) = ~a~c~d Heavy and tedious Reduction using graphical Karnough maps –Basic product terms: ~a~b~c~d + ~ab~c~d + ~ab~cd + ~abc~d + abcd + abc~d + a~bcd + a~bc~d –Reduced expression: ~a~c~d + ~ab~c + ac + bc~d = ~a~c x (~d + b) + c x (a + b~d) Quick and elegant, but for more than four variables it gets complicated Today: Logic synthesis Only one bit changing c,d 10 01 00 11 10 110100a,b 1 1 0 0 0 1 0 0 0 0 1 1 0 1 1 1 Alternative: bc~d or ~ab~d

7 December 2003J.Christiansen/CERN6 Which gates are really needed ? How many different types of gates are needed to implement any given logical function ? : Inv And Or So why is this not used in practice ? Too slow or too large area Different drive capabilities also needed (buffers) Memory elements can also be made from this

8 December 2003J.Christiansen/CERN7 Implementing logic with memories ? RAM or ROM can be used to implement logic operations: Look Up Table (LUT) Logic Map any given combination into required output InputsOutput --0000 0 --0001 0 --0010 1 --0011 1 --0100 0 -------- - --1111 0 Address (input) Data (output) Address decoding logic + memory array used to implement required function For most applications Look up tables not efficient (size and speed) Special applications: Special encoders/decoders Programmable logic in FPGA’s

9 December 2003J.Christiansen/CERN8 Timing of digital circuits Load Delay Gate delay depends on: Type of gate Number of inputs Which input Transition ( 0 -> 1 or 1 -> 0 ) Output load Input slew rate Temperature Supply voltage Process parameters Technology Gates Sequential circuits Clock DQ Setup: Input data must have stabilized certain time before clock Hold: Data must not change within certain time after clock Clock Data Timing requirements

10 December 2003J.Christiansen/CERN9 Timing examples Data arriving too late (too long logic delay) Data arriving too early (clock skew problem) Asynchronous input signal (meta-stability problem) DQDQ Logic Clk Q D Logic delay DQDQ Clk1 D Flip-flop delay delay Clk2 DQ Clk Data from asynchronous system Delay Sample point Output finally resolves to 0 or 1

11 December 2003J.Christiansen/CERN10 Wires also have delays Capacitive loading of gate (affects gate delay but can not be considered a wire delay) Propagation delay because of distributed L-C –Wire has delay. –Wire has characteristic impedance which may cause reflections. –Normally not important inside chips but must be taken into account for signal exchange between chips. –If wire resistance also signal attenuation R-C delays –Thin wires have resistance and capacitance –Gives wire delay Reduces signal slew rate Complicated delay calculation for wire networks Z

12 December 2003J.Christiansen/CERN11 Logic values Digital logic only works with Logic 0 and Logic 1 Logic values represented by voltages Noise Crosstalk Voltage drops

13 December 2003J.Christiansen/CERN12 State machines Used to go through sequence of events based on inputs. State evaluation/change every clock cycle. Best represented by state transition diagrams. Implemented with state memory (flip- flops) and state transition logic. Different encodings: –Binary ( 000, 001, 010, 011, 100, ) –Gray code O nly one bit changes in any state transition –One hot ( 001, 010, 100) One and only one bit actively set (fast) –Counters are a type of state machine with simple algorithmic state transitions. A B C D E 0 1 2 3 4 5 6 7 Counter State register State Transition logic Inputs Clock Reset

14 December 2003J.Christiansen/CERN13 Pipelining A Pipeline is used to increase operating speed of a digital circuit: –Increases operation frequency –Increases Latency (slightly) Logic Storage Clock Logic D Storage Logic C Storage Logic B Storage Logic A Storage ABCD t logic t stor F1 = 1 / ( t logic + t stor ) Latency1 = t logic + t stor F2 = 4 x F1 Latency2 = Latency1 + 3x t stor Clock Wave pipelining: Use delays as short term data storage

15 December 2003J.Christiansen/CERN14 Data processing In data processing applications a separation is normally made between the real data processing and the control of the processing. –Data path: Data exchange (data busses, data multiplexers, etc.), Data storage (memory, pipeline, register file, etc.), Data processing ( additions, multiplications, shifts, etc.) –Control: State machines that determines the control of the of the data path Control Unit 1 Unit 2 Unit 3 Unit 4 Command Status Data path Register file Address generation path

16 December 2003J.Christiansen/CERN15 Data path control State machines (used in hardwired RISC processors) Micro code (used in CISC processors) A B C D E A B C D E B B B Micro code memory Command Data path statusData path control AddressData Clock Command (Strongly simplified)

17 December 2003J.Christiansen/CERN16 Digital implementation TypeYearComment Transistors50 Descreete logic60 - 80TTL, FAST, ECL, NMOS, CMOS PAL70 - 80Programmable, Simple functionality PLD80 - 90Programmable, Limited functionality CPLD90 - ? Programmable, Complex logic FPGA90 - ?(Re)-Programmable, Very complex logic, Cheap development, Limited large scale production cost ASIC80 - ?Very high performance, Very large complexity, Expensive development, Cheap large scale production DSP/processor80 - ? PAL: Programmable Array Logic PLD: Programmable Logic Device CPLD: Complex Programmable Logic Device FPGA: Field Programmable Gate Array DSP: Digital Signal Processor ASIC: Application Specific Integrated Circuit Large flexibility, Data processing, Low–high performance (still used for RF and power)

18 December 2003J.Christiansen/CERN17 IC Technologies Bipolar: –High speed, Good analog performance, Limited integration NMOS: –First MOS ( Metal Oxide Semiconductor ) technology –Limited performance, High static power, Limited integration CMOS –Complementary MOS with zero static power –Very high integration –Very high performance in modern CMOS –Frequent introduction of improved technologies (every 2-3 years) –Other improvements: BiCMOS: Both Bipolar and CMOS on same chip SOI (Silicon on Insulator): Isolated devices and lower parasitic capacitances SiGe (Silicon Germanium): Improved transistor speed by incorporating Ge. Exotic: GaAs, HEMT, –Very high speed ( RF, High speed telecommunication, etc.) –Low integration, Low yield

19 December 2003J.Christiansen/CERN18 All this is just “simple” binary thinking There are only 10 types of people in this world: Those who understand binary And those who don’t


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