1. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 1 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Bruce Mayer, PE Registered Electrical & Mechanical Engineer BMayer@ChabotCollege.edu Engineering 43 Chp 3.1b Nodal Analysis

2. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 2 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Ckts with Voltage Sources  Need Only ONE KCL Eqn  The Remaining Eqns From the Indep Srcs  Solving The Eqns  3 Nodes Plus the Reference. In Principle Need 3 Equations... But two nodes are connected to GND through voltage sources. Hence those node voltages are KNOWN

3. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 3 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example R1 = 1k; R2 = 2k, R3 = 1k, R4 = 2k Is1 =2mA, Is2 = 4mA, Is3 = 4mA, Vs1 = 12 V  Need Only V 1 and V 2 to Find V o  Known Node Potential  Now KCL at Node 1  Find V o  To Start Identify & Label All Nodes Write Node Equations Examine Ckt to Determine Best Solution Strategy  Notice

4. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 4 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example cont. R1 = 1k; R2 = 2k, R3 = 1k, R4 = 2k Is1 =2mA, Is2 = 4mA, Is3 = 4mA, Vs = 12 V  At Node 4  To Solve the System of Equations Use LCD-multiplication and Gaussian Elimination  At Node 2

5. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 5 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example cont.  The LCDs *2k (1) (2) (3)  Now Add Eqns (2) & (3) To Eliminate V 4 (4)  Now Add Eqns (4) & (1) To Eliminate V 2  BackSub into (4) To Find V 2  Find V o by Difference Eqn

6. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 6 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis SuperNode Technique  Consider This Example  Conventional Node Analysis Requires All Currents At A Node  2 eqns, 3 unknowns... Not Good Recall: The Current thru the V src is NOT related to the Potential Across it  But Have Ckt V-Src Reln  More Efficient solution: Enclose The Source, And All Elements In Parallel, Inside A Surface. –Call That a SuperNode SUPERNODE

7. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 7 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Supernode cont.  Apply KCL to the Surface  Now Have 2 Equations in 2 Unknowns  Then The Ckt Solution Using LCD Technique See Next Slide SUPERNODE The Source Current Is interior To The Surface And Is NOT Required  Still Need 1 More Equation – Look INSIDE the Surface to Relate V 1 & V 2

8. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 8 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Now Apply Gaussian Elim  The Equations  Mult Eqn-1 by LCD (12 kΩ)  Add Eqns to Elim V 2  Use The V-Source Rln Eqn to Find V 2 SUPERNODE

9. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 9 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Find the node voltages And the power supplied By the voltage source To compute the power supplied by the voltage source We must know the current through it: @ node-1 BASED ON PASSIVE SIGN CONVENTION THE POWER IS ABSORBED BY THE SOURCE!!

10. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 10 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Illustration using Conductances  Write the Node Equations KCL At v 1  At The SuperNode Have V-Constraint v 2 − v 3 = v A  KCL Leaving Supernode  Now Have 3 Eqns in 3 Unknowns Solve Using Normal Techniques   

11. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 11 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Example  Find I o  Known Node Voltages  Now KCL at SuperNode SUPERNODE  The SuperNode V-Constraint  Or

12. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 12 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Student Exercise  Lets Turn on the Lights for 5-7 min  Students are invited to Analyze the following Ckt Hint: Use SuperNode  Determine the OutPut Current, I O

13. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 13 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Numerical Example  Find I o Using Nodal Analysis  Known Voltages for Sources Connected to GND  Now KCL at SuperNode  The Constraint Eqn SUPERNODE  Now Notice That V 2 is NOT Needed to Find I o 2 Eqns in 2 Unknowns  By Ohm’s Law

14. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 14 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Complex SuperNode  Write the Node Eqns  Set UP Identify all nodes Select a reference Label All nodes  Nodes Connected To Reference Through A Voltage Source  Eqn Bookkeeping: KCL@ V 3 KCL@ SuperNode, 2 Constraint Equations One Known Node supernode  Voltage Sources In Between Nodes And Possible Supernodes Choose to Connect V 2 & V 4

15. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 15 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Complex SuperNode cont.  Now KCL at Node-3 supernode  Constraints Due to Voltage Sources  Now KCL at Supernode Take Care Not to Omit Any Currents V s1 V s2 V s3  5 Equations 5 Unknowns → Have to Sweat Details

16. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 16 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Dependent Sources  Circuits With Dependent Sources Present No Significant Additional Complexity  The Dependent Sources Are Treated As Regular Sources  As With Dependent CURRENT Sources Must Add One Equation For Each Controlling Variable

17. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 17 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Numerical Example – Dep I src  Find I o by Nodal Analysis  Notice V-Source Connected to the Reference Node  KCL At Node-2  Sub I x into KCL Eqn  Mult By 6 kΩ LCD  Then I o  Controlling Variable In Terms of Node Potential

18. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 18 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Dep V-Source Example  Find I o by Nodal Analysis  Notice V-Source Connected to the Reference Node  SuperNode Constraint  KCL at SuperNode  Mult By 12 kΩ LCD  Controlling Variable in Terms of Node Voltage

19. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 19 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Dep V-Source Example cont  Simplify the LCD Eqn  By Ohm’s Law

20. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 20 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis Current Controlled V-Source  Find I o  Supernode Constraint  Controlling Variable in Terms of Node Voltage  KCL at SuperNode  Multiply by LCD of 2 kΩ  Recall  Then  So Finally

21. BMayer@ChabotCollege.edu ENGR-43_Lec-03-1b_Nodal_Analysis.ppt 21 Bruce Mayer, PE Engineering-43: Engineering Circuit Analysis WhiteBoard Work LLet’s Work This Problem FFind the OutPut Voltage, V O IXIX